本論文中，我們將討論無邊界接觸窗與自行對準矽化物的製程及矽化金屬與非矽化金屬電阻在毫微米以下積體電路之應用。
首先，吾人將開發無邊界接觸窗(borderless contact)與自行對準矽化物的製程並研究其特性。採用較低溫之化學氣相沈積法(CVD)形成的氮氧化矽層(SiOxNy)做為蝕刻之終止層。並研究增加的雙重n+ 及p+ 源/汲極離子佈植法對元件特性之影響；所增加的雙重n+ 及p+ 離子佈植源/汲極(DDD)可以有效的降低遺漏電流，這些遺漏電流大部份是來自無邊界接觸窗，其造成電流由淺溝渠隔離結構遺漏；因此，須增大無邊界接觸窗之蝕刻製程。此外，採用低溫且快速沉積之方法，並不會影響所使用矽化金屬層的片電阻 (sheet resistance)亦不會產生凝聚或不均勻的現象。
接著，吾人提出雙重離子佈植法(DII)在鈦金屬矽化合物之應用。此雙重離子佈植法不須增加光罩，而是結合非晶矽化鍺（或砷）離子佈植法(PAI)及矽離子混合法(Si ion-mixing)之技術。採用此雙重離子佈植法的技術，可以獲得比較低且穩定的n+ 及p+ 閘極及源/汲極矽化鈦片電阻值。再者，雙重離子佈植法的片電阻值會比單一非晶矽化鍺（或砷）離子佈植法或矽離子混合法低5% 至10%。此外，雙重離子佈植法中的矽離子混合法可以有效的降低遺漏電流。再者，應用非晶矽化鍺（或砷）離子佈植法在鈷金屬矽化合物之探討。吾人亦採用雙重離子佈植法之鈦及鈷金屬矽化合物成功的開發0.2mm互補式金屬半導體(CMOS)元件。
本文亦提出應用於混合訊號電路非矽化金屬多晶矽層的電阻值特性之研究。基於前文所述，非矽化金屬多晶矽層的電阻兩端的矽化金屬鈦（或鈷）亦採用無邊界接觸窗結構之設計。吾人提出一簡單的理論模式用於分析及計算非矽化金屬多晶矽層的電阻參數，例如多晶矽電阻電性寬度(DW)、介面電阻值(Rinterface)及本體電阻值(Rbulk)。在毫微米積體電路中，此理論模式幫助電路設計者精確的計算非矽化金屬多晶矽層的電阻值。再者，吾人亦提出及探討非矽化金屬多晶矽層電阻的電壓係數(VCR)、電阻的溫度係數(TCR)及電阻匹配(Rmis)。實驗結果顯示，以上的電阻模式與實驗數據吻合。
接著，本論文亦提出一新電阻結構以應用於毫微米以下的積體電路之設計。由前理論模式得知，多晶矽層電阻的電壓係數(VCR)受到介面電阻值很大的影響，此一新電阻結構可有效的降低多晶矽層的介面電阻值。此一新電阻結構具有較大的有效介面寬度，可用以抑制多晶矽層電阻的電壓係數受到介面電阻值的影響程度。
另一方面，我們亦研究在不同的電流及溫度應力效應下，非矽化金屬多晶矽層電阻的可靠度。由實驗得知最大的電流密度會隨著非矽化金屬多晶矽層電阻寬度的增加而增加，多晶矽層電阻的失敗時間(TTF)會隨著電流及溫度應力的增加而減短。吾人提出一個經驗方程式用以預測多晶矽層電阻之最大電流密度及疲勞壽命。在一固定的直流電流密度(1.0×106A/cm2)及不同的溫度下，計算出n+ 及 p+ 多晶矽層電阻的活化能(Ea)分別為0.67及0.48 eV。再者，在一固定的溫度(473K)及不同的直流電流密度下，計算出n+ 及 p+ 多晶矽層電阻的電流依賴因子分別為1.57x10-5及1.30x10-5 cm2/A。因此，可以精確的提供電路設計者及製程工程師對於多晶矽層可靠度之探討及預測最大電流密度與疲勞壽命。

In this dissertation, we will study borderless contact (BLC) process of the silicide and non-silicide technologies for sub-quarter micron ULSI CMOS applications. The characteristics of a new and improved borderless contact (BLC) are studied. A low-temperature and high deposition rate CVD-oxynitride (SiOxNy) film is used to act as the selective etching stop layer. The additional n+ and p+ source-drain double implant structure (DIS) are employed in the studied device. The additional n+ and p+ DIS can reduce the junction leakage current, which is usually enhanced by BLC etching near the edge of shallow trench isolation (STI). The process window is enlarged. Furthermore, the employed low-thermal oxynitride and high deposition rate can improve the salicide thermal stability and avoid the salicide agglomeration. In addition, double ion-implant (DII) Ti-salicide with the arsenic pre-amorphization implantation (PAI) and Si ion-mixing implant have been developed successfully and studied. The DII technique is combined by germanium (or arsenic) PAI and Si ion-mixing implant without additional lithography process. The sheet resistances both of n+ and p+ polysilicon resistors with DII process are decreased especially in the narrow gate width regime. Based on this technology, the good performances of uniform Ti-silicide formation, low and narrow distribution of sheet resistances both on n+/p+ poly-gate and source/drain diffusion layers are obtained. In addition, for DII process, the sheet resistances are lowered by 5 to 10% than those of PAI or Si ion-mixing only. Furthermore, the junction leakage current is reduced when the Si ion-mixing process is employed. Experimentally, based on the studied PAI and Si ion-mixing techniques, high-performance 0.2mm CMOS devices are fabricated successfully.
The characteristics of non-silicide polysilicon resistors in sub-quarter micron CMOS mixed-mode applications are reported in this thesis. Based on the presented sub-quarter micron CMOS borderless contact, both n+ and p+ polysilicon resistors with Ti- and Co-silicide self-aligned process are used at the ends of each resistor. A simple and useful model is proposed to analyze and calculate some important parameters of polysilicon resistors including electrical delta W (DW), interface resistance Rinterface, and bulk sheet resistance Rbulk. This approach can substantially help engineers in designing and fabricating the precise polysilicon resistors in sub-quarter micron CMOS technology. In addition, the characteristics of voltage coefficient of resistor (VCR), temperature coefficient of resistor (TCR), and resistor mismatching (Rmis) are also studied.
In addition, a new and improved structure of polysilicon resistor for sub-quarter micron CMOS device applications is demonstrated and studied. A simple model is proposed to analyze its important parameters such as the voltage-dependent bulk sheet resistance, interface resistance, and VCR. An anomalous voltage-dependent characteristic of overall resistance is found mainly resulting from the existence of interface resistance. The proposed structure of polysilicon resistor with a larger effective width of interface region shows substantial suppression of the voltage-dependent resistance deviation caused by interface resistance. The reduction of VCR value is also obtained for the new structure. Consequently, from experimental results, the proposed structure can be used in precise (lower VCR) polysilicon resistors.
The effects of electrical and temperature stress on polysilicon resistors reliability in sub-quarter micron CMOS applications have been studied. The maximum current density (Jmax) is increased with the decrease of polysilicon resistor width W. The time-to-fail (TTF) value of the polysilicon resistor is decreased with increasing the electrical and temperature stress. A simple empirical formula is proposed in this study to predict the Jmax and lifetime of polysilicon resistors. Under a fixed dc current density (1.0×106A/cm2), the activation energies (Ea) for n+ and p+ polysilicon resistors at different temperature are 0.67 and 0.48 eV, respectively. In addition, at a fixed temperature of 473K, the current factors for n+ and p+ polysilicon resistors are 1.57x10-5 and 1.30x10-5 cm2/A, respectively, under different dc current densities. Therefore, these precise reliability performances offer the promise for ULSI design and fabrication.

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