目前IEEE 802.11n被許多無線通訊應用廣泛的採用，而為了達到更高的資料處理速度，IEEE 802.11ac目標是能夠達到1Gbps的處理速度。雖然有很多文獻在探討如何設計一個類循環低密度同位元碼(Quasi-cyclic low-density parity-check code)解碼器，但卻很少可以在不同的資料處理速度下，提供一個有效率且彈性的硬體設計方法。
本篇論文中，我們提出了一個安排記憶體配置的方法，有效解決，假如使用單位矩陣區塊設計的解碼器同時處理多個單位矩陣區塊，記憶體會遇到的資料讀取衝突的問題。另一方面，我們實現了適用於IEEE 802.11n標準全模式解碼器之位移電路。所提出之位移電路只需要一個簡單的桶形移位器(Barrel shifter)與低複雜的判斷單元，即可完成適合IEEE 802.11n中所定義的三個不同大小的展開矩陣。此外，此設計亦可在無資料擁擠的前提下，平行處理多筆資訊的位移。其中，利用循環字首(Cyclic prefix)的概念以及三種展開矩陣的倍數關係，在位移資料時，我們發現在多餘的輸入埠複製有用的資訊與額外的位移量，可以大幅地降低原本所需的判斷單元複雜度。上述提出的兩個方法可以幫助我們有效率的設計一個多模式的類循環低密度同位元檢查碼解碼器。

Currently, IEEE 802.11ac, which is developed from IEEE 802.11n, is aimed to achieve the higher throughput rate, at least 1 Gbps. Although there are lots of approaches to design quasi-cyclic low-complexity parity-check (QC-LDPC) decoders, few efficient methods have not been found to construct QC-LDPC decoders with the flexibility of the throughput rate.
In this thesis, a method for memory arrangement is proposed to solve the memory access conflict from multiple blocks processed concurrently in the block-parallel decoder. Furthermore, a modified shift network for the full-mode LDPC decoder is proposed for IEEE 802.11n applications. To significantly reduce complexity of shift network architecture, the concept of cyclic prefix and the relationship among three expansion factors of parity check matrices are adopted when no data congestion occurs in parallel decoding messages routing. Additionally, additional circular shift and appropriate duplication in redundant input ports of the barrel shifter help us to reduce the complexity of decision units. Therefore, the proposed shift network architecture is only composed of a simple barrel shifter and a low-complexity block selector. In conclusion, a full-mode QC-LDPC decoder can be efficiently designed using the above two approaches.

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