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| 研究生： |
黃凱立 Huang, Kai-Li |
|---|---|
| 論文名稱： |
應用於60GHz毫米波之CMOS壓控震盪器與混頻器設計 Design of CMOS Voltage-Controlled Oscillator and Mixer for 60GHz Millimeter-Wave Applications |
| 指導教授： |
黃尊禧
Huang, Tzuen-Hsi |
| 學位類別： |
碩士 Master |
| 系所名稱： |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年： | 2009 |
| 畢業學年度： | 97 |
| 語文別： | 英文 |
| 論文頁數： | 129 |
| 中文關鍵詞： | 混頻器 、壓控震盪器 、高頻 、相位雜訊 |
| 外文關鍵詞： | CMOS, VCO, Mixer, 60GHz |
| 相關次數： | 點閱：73 下載：6 |
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以往高頻的電路許多都採用SiGe或是III-V半導體製程來製作，因為這些製程比起CMOS製程所提供的元件特性較好。不過這些製程在成本上比CMOS多出不少。基於成本以及整合性的考量，我們仍希望電路能以CMOS製程來製作。隨著半導體技術的不斷成長，CMOS元件的特性也越來越好，這將有助於我們在高頻電路上的設計，即使如此，使用CMOS來製作操作頻率約為60GHz左右的電路仍有不少的挑戰需要克服。
在這篇論文，我們首先實做了1個應用於V-band之雙推式壓控震盪器，由於製程上的限制，使用CMOS 0.18um將無法製作出震盪於此頻率的振盪器，因此我們使用了雙推式的架構，利用此振盪器的2倍頻諧波，使我們可以得到一V-band的高頻訊號來源。量測的結果顯示，此電路的震盪頻率為52.74 GHz到55.42 GHz，相位雜訊在位移為1MHz的狀態下具有-94.45dBc/Hz的表現，整體FOM為-176.23 dBc/Hz。
緊接著我們利用CMOS 0.13um製程來製作一個應用於V-band之雙閘級混頻器，此種架構在電路的觀點上來看即為一個cascode架構，此架構的混波方式與一般傳統的Gilbert-cell不同，是利用LO訊號來改變下面電晶體的gm藉此產生混波的動作，所以每顆MOS的偏壓點對於此電路的效能都有著很大的影響，根據理論以及模擬後結果的驗證，此電路必須使它操作在low-noise mode以得到最佳的效能。此電路的特色為低電壓的設計，最高的偏壓僅為0.9V，同時又能提供微幅的轉換增益以及不錯的線性度表現。再來我們又製作了一顆預期應用於實驗室提出之60 GHz WPAN與3-10 GHz UWB共存系統的寬頻帶混頻器，以往文獻上所提的混頻器大多IF皆為定頻，此電路為了符合系統上的需求IF必須擁有1.8 GHz以上的頻寬。為了達到此目標，我們在Gilbert-cell的負載級採用了切換式電容陣列搭配電感所形成的共振腔來形成此電路的負載，在模擬的結果上顯示，此方法確實能在IF端擁有約1.8 GHz寬的平坦增益。除此之外，此電路為了量測上以及未來應用的考量，在電路架構中也整合了一寬頻的balun，以提供在輸入端作一寬頻的匹配並確實的在量測上提供將輸入訊號分為2個相位差為180度的訊號。綜合以上設計，本論文將顯示使用CMOS 0.13um製程實作60GHz毫米波電路的可行性，在未來若能使用CMOS 90nm製程相信能做出具有更佳效能的電路。
The previous published circuits operate at high frequency which make up by SiGe or III-V compound semiconductor technology, because those processes have better device characteristics compare to CMOS process but it also exist a drawback is higher cost. Base on the considerations of cost and integration we still prefer implement circuits by CMOS process. With the progress of CMOS technology, the characteristics of device are better and better. This phenomenon has benefits when we design circuits at higher frequencies. Even though it still exists many challenge wait us to overcome when we practice circuits around 60 GHz by CMOS process. In this paper, we implement a push-push VCO for V-band applications first. Because the limitation of process, the VCO core can’t oscillate at V-band when we using CMOS 0.18um process. In order to achieve our target, we using push-push structure to extract the second-order harmonic of VCO and get a V-band output signal. The measured results of this VCO show the tuning range from 52.74 GHz to 55.42 GHz and phase noise is -94.45 dBc/Hz at 1MHz offset frequency.
After that we implement a dual-gate mixer for V-band applications by CMOS 0.13um process. This structure is equal a cascode structure in circuit’s viewpoint. The mixing theorem of this structure is differs with traditional Gilbert-cell mixer, it mixed by using LO signal to vary the gm of lower MOS. Therefore, the bias conditions of each MOS are exist huge influence in the performance of circuit. According to the theorem and simulation results showed, if this mixer want to gain best performance then it should be operate at low-noise mode. The characteristic of this circuit is the design with low supply voltage. It has capability to provide small conversion gain and good linearity even if the highest supply voltage only 0.9V. Furthermore, we practice a wide band 60 GHz mixer for proposed 60 GHz WPAN and UWB co existence system. The previous published works almost fit their IF at single frequency, but our proposed mixer must have bandwidth over 1.8 GHz. For achieve this purpose, we put a switchable capacitor array to collocating inductor and form a resonator to treat as load of this mixer. The simulation results prove this concept works which have a flatness gain with 1.8 GHz bandwidth indeed. Besides, we consider the situation of measurement and applications in the future so we integrate a broadband balun into this design. This balun provide input matching and split input signal to two signals with differential phase. According above designs we have capability to prove the circuits operate around 60 GHz and made by CMOS 0.13um process is practicable. In the future, we believe better circuits will be implemented by CMOS 90nm process.
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校內：2012-08-25公開校外：2012-08-25公開