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研究生： 趙安生
Chao, An-Sheng
論文名稱： 逐漸逼近式類比數位轉換器之內建自我測試電路設計
Design of Built-In Self-Test for Successive Approximation Register Analog-to-Digital Converters
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 博士
Doctor
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2014
畢業學年度： 102
語文別： 中文
論文頁數： 83
中文關鍵詞： 類比數位轉換器 、內建測試設計
外文關鍵詞： ADC, DfT
相關次數： 點閱：52  下載：2 
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    • 本論文主要針對逐漸逼近式類比數位轉換器開發內建自我測試電路，以完成線性度測試，包含微分非線性及積分非線性。
    一個嵌入式測試訊號源經設計並實作於逐漸逼近式類比數位轉換器內部，以實現一個可測性設計，其基本原理乃是利用逐漸逼近式類比數位轉換器內部之數位類比轉換器，以實現一個區段線性的測試訊號源，基於數位類比轉換器硬體之重覆使用，此一訊號源僅需少量額外面積，相較於逐漸逼近式類比數位轉換器，此內建訊號源之可測性設計僅增加12.4%之面積。另外，若將此可測性設計與圖樣產生器及輸出響應分析器結合，則可完成內建自我測試之功能。
    另外，為了再進一步降低於內建自我測試電路中設計訊號源的需求，本論文亦提出一個藉由量化逐漸逼近式類比數位轉換器內電容陣列比例的方法，達到不需額外訊號源，而完成線性度估計。首先，由圖樣產生器產生數位控制碼，以設定逐漸逼近式類比數位轉換器內電容陣列，使電容陣列兩端產生相應於個別電容比例之電壓差，此電壓差經由設計於比較器上之量化電路，進行量化，接著配合所推導出來的映射關係，輸出線性度估計之結果，包括微分非線性及積分非線性，而完成整體內建自我測試電路之設計。

    In this dissertation, we develop a built-in self-test (BIST) design for successive approximation register (SAR) analog-to-digital converters (ADCs) to accomplish the linearity tests, including the differential nonlinearity (DNL) and integral nonlinearity (INL).
    The design for testability (DfT) circuit combines the embedded stimulus generator and the SAR ADC. The internal digital-to-analog converter (DAC) in the SAR ADC is controlled by digital patterns to generate the piecewise linear signal as the test stimulus. The embedded stimulus generator reuses the internal DAC, thus the hardware cost is alleviated. The DfT circuit occupied additional 12.4% area of the SAR ADC. The DfT circuit, the pattern generator (PG), and the output response analyzer (ORA) are combined as the BIST design.
    Moreover, another test method is proposed to estimate the linearity without the test stimulus generator by quantifying the capacitance ratios in the internal DAC of the SAR ADC. Firstly, the pattern generator issues the digital pattern to set up a capacitance ratio in the capacitor array. The voltage difference across the capacitor arrays is proportional to the capacitance ratio and quantified by the proposed quantifying circuit, which is combined with the comparator in the SAR ADC. By applying the derived equations between capacitance ratios and the DNL, the linearity test results of the SAR ADC under test, including DNL and INL, are estimated in the BIST design.

    List of Tables xiii List of Figures xv CHAPTER 1 Introduction 1 1.1 Introduction 1 1.2 Organization of the Dissertation 5 CHAPTER 2 Basics of Analog-to-Digital Converter Testing 7 2.1 Static ADC Testing 8 2.1.1 Specifications for Static ADC Testing 8 2.1.2 Back-to-Back Test Method 10 2.1.3 Histogram (Code Density) Test with Linear Ramp Stimulus 11 2.2 Dynamic ADC Testing 13 2.2.1 SNR, SINAD, and ENOB 13 2.2.2 FFT-Based Test 13 2.3 Previous Work 14 2.3.1 Selective Code Measurement 14 2.3.2 Stimulus Error Identification and Removal (SEIR) 16 2.3.3 DfT Circuit for Reducing Test Time 19 2.3.4 MCT Testing Method 20 2.3.5 DfT Circuit for Sigma-Delta ADC 21 2.4 Summary 23 CHAPTER 3 Embedded Stimulus Designs for SAR ADCs 25 3.1 Architecture and Design Concept for Missing Code Test 26 3.1.1 D2D Test 27 3.2 Architecture and Design Concept for Linearity Test 28 3.2.1 Operation and Modification of Conventional Bottom-Plate Sampling SAR ADCs 28 3.2.2 Modification on Differential Top-Plate Sampling SAR ADCs 32 3.2.3 Average Number of Hits per Code 34 3.2.4 Impacts of FDAC Nonlinearity 35 3.2.5 Discussion on Static-Linearity Errors 36 3.3 Implementation of Building Blocks 37 3.3.1 Analog Components 37 3.3.2 Digital Components 39 3.3.3 Overhead 39 3.4 Measurement Results 41 3.4.1 Dynamic Performance and Figure-of-Merit 42 3.4.2 Static Performance 42 3.4.3 Comparison Table 45 3.5 Summary 46 CHAPTER 4 Capacitance-Ratio Quantification Design for Linearity Test 47 4.1 Overview of Proposed Test Method 47 4.1.1 Relation between Capacitance Ratio and DNL 48 4.1.2 Capacitance-Ratio Quantification 53 4.1.3 Built-in Self-Test Design 55 4.1.4 DNL Estimation from Capacitance Ratios 56 4.2 Implementation of Building Blocks 59 4.2.1 SAR ADC 59 4.2.2 Quantification Unit 59 4.2.3 Pattern Generator 61 4.2.4 Output Response Analyzer 61 4.3 Simulation Results and Discussions 62 4.3.1 Area Overhead 62 4.3.2 Dynamic Performance 63 4.3.3 Static Performance for On-chip Verification 64 4.3.4 Static Performance with Capacitor Mismatch at Process Corners 70 4.3.5 Comparator Offset 72 4.3.6 Testable Range 72 4.3.7 Test Time Estimation 72 4.4 Summary 74 CHAPTER 5 Conclusions and Future Work 75 5.1 Conclusions 75 5.2 Future Work 76 REFERENCES 77 PUBLICATION LIST 83

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