由於在許多論文或研究中，皆會發現帶隙電壓參考電路受製程影響嚴重，導致溫度係數的量測結果不如模擬預期，因此在本論文研究中，我們將探討製程變化的影響，並提出一個具參考性的模擬方式來分析製程變異的影響以及兩種具溫度補償和製程變異校正之帶隙電壓參考電路。第一種改善電路為電阻trimming方式之帶隙電壓參考電路，主要利用四個開關控制四種不同阻值的電阻來實現一階補償的校正。第二種改善電路為抗電阻製程變異之帶隙電壓參考電路，電路針對電阻製程變異影響設計二階補償電路，其中二階補償電路包含PTAT電流補償電路和CTAT電流補償電路。
本篇論文採用TSMC 0.18μm 1P6M CMOS製程，電阻trimming方式之帶隙電壓參考電路從0度到120度時的最好的溫度係數量測結果為5.35 ppm/℃，PSR在100 Hz與1K Hz時量測結果分別為-55.4 dB與-46.3 dB，電壓1.8 V時電流消耗為41.6 μA。另外，抗電阻製程變異之帶隙電壓參考電路從0度到120度時的最好的溫度係數量測結果為12.22 ppm/℃，PSR在100 Hz與1K Hz時量測結果分別為-39.6 dB與-40.7 dB，電壓1.8 V時電流消耗為58.3 μA。總面積大小為1.105*1.1 mm2。

In this study, we present two high precision bandgap voltage reference (BGR) circuits with calibration technique of process variation. The calibration technique of first order compensation by four switches using to control the different resistance values of resistors in the first proposed circuit. Moreover, we also present a new compensation circuit in the second proposed circuit, which can automatic calibrate the reference voltage of BGR circuit when BJTs and MOSFETs operate in TT corner and Resistors operate in any kind of process corners. The measurement results of BGR with calibration technique of resistance trimming show that the best temperature coefficient is 5.35 ppm/˚C at temperature from 0 ˚C to 120 ˚C, the quiescent current consumption is 41.6 μA with a power supply of 1.8 V. Furthermore, the measurement results of BGR with calibration technique of resistance process variation show that the best temperature coefficient is 12.22 ppm/˚C at temperature from 0˚C to 120˚C, the average quiescent current consumption is 58.3 μA with a power supply of 1.8 V. Total active area of chip is 1.22 mm2.

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