本篇論文中描述具有位階變換背景校正技術的四位元互補金氧半快閃式類比數位轉換器。在此系統中，增加了一組比較器及電組切換開關並且利用隨機相位的切換來製造出切換前及切換後兩種狀態。在此兩種狀態對於同一比較器而言為參考電壓偏移1LSB 量值。由於內部比較器會有製程不匹配所產生的偏移問
題。在切換前和切換後時，輸入信號落於相同溫度計編碼的機率將不相同。然後，利用漣波式計數器電路來計算兩種狀態所產生出來的機率並且藉由數位類比轉換器來將偏移量做消除。在此，漣波式計數器只有輸入信號落於該溫度計編碼時才計數。所以，並非所有計數器都同時在做校正動作。最後，經由一段時間的背景校正，此系統的效能將藉此獲得改善並且維持住。
這個類比數位轉換器的實現是採用0.13μm，1P8M 互補金氧半混合信號製程，有效面積為0.027mm2。佈局後的模擬結果驗證此類比數位轉換器在輸入信號為435MHz，操作頻率為1GHz 時，具有3.83 位元的有效解析度。整個晶片在1.2 伏特的操作電壓下，消耗5mW 的功率。

A 4-bit flash ADC with step-shifted background calibration method is proposed in this thesis. This system would increase one comparator, switches for resistor
ladder and use the random phase generator to generate shifted and non-shifted states. For the same comparator, its reference voltage would shift 1LSB in the two states.
Because of the offset due to device mismatch, the probability of the input signal hitting into the same thermometer in shifted and non-shifted states would not be the same. Then, the system calculates the probability of the two states by ripple counter and applies the DAC circuit to cancel the offset. The counter would only work
where the input signal hits in the thermometer code. Therefore, all of the counters wouldn’t work at the same time. Finally, the performance of the system would
improve and keep after some calibration periods.
This ADC is fabricated in a 0.13μm 1P8M CMOS process. The active area is only 0.027mm2. The ADC achieves a measured ENOB of 3.83b for a 435MHz input at 1GS/s. The power consumption (including clock buffer and resistor ladder) is 5mW at 1GS/s.

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