本論文發表一種新穎的以Pseudo-CMOS為基礎之全平行內容可定址記憶體(Content-Addressable Memory, CAM)架構設計，以達到低功率及高速的資料搜尋為目的。相較於傳統的內容可定址記憶體電路設計，這種基於Pseudo-CMOS邏輯架構的設計技巧，不但可以避免動態電路的諸多缺點，以及降低整體電路的功率消耗和增加比對速度，更可降低電路設計時的複雜度及不規則性，使電路可以快速的開發並整合在相關的應用中。
為了達到低功率消耗及低電壓的需求，本論文設計了一個以Pseudo-CMOS為基礎之二元內容可定址記憶體(BCAM)電路設計，該架構在內容可定址記憶體電路應用中，具有低功率消耗及高比對速度特性。而基於所提出的Pseudo-CMOS邏輯架構，本論文更提出一種四元內容可定址記憶體(QCAM)架構設計，此電路具備四元狀態特性，除了具備低功率消耗及高比對速度特性之外，亦提供一個比傳統三元內容可定址記憶體更有彈性的功能選擇。
整個電路皆已在TSMC 0.35 μm SPQM CMOS的製程下製作並驗證完成。以一個內容大小為128 × 30的BCAM，經由實際量測結果得知本論文所提出的電路架構在3.3 V的電壓供應下，工作頻率達85 MHz (含輸出/入接腳延遲)，且功率消耗低於23 mW。除此之外，由量測中亦可發現本電路在低達1.5 V的供應電壓下，工作頻率可達32 MHz。另一方面，一個容量大小為128 × 30的QCAM，在3.3 V的電壓供應下，其工作頻率亦可達到71 MHz，且功率消耗低於29 mW。在低達1.4 V的供應電壓下，工作頻率可達15 MHz。

This thesis presents a novel VLSI architecture for a fully parallel content- addressable memory with low-power, and high-speed features. This design is based on a proposed static pseudo-CMOS logic structure that not only improves the comparison speed of the CAM word circuit, but also reduces power dissipation of the CAM system.

In addition, the static pseudo-CMOS logic structure does not require clock signal to drive overall circuit, thus the clock skew, noise margin, and the charge sharing issues in the traditional dynamic CAM circuit are eliminated. In order to reduce the operating voltage and hardware cost of pseudo-CMOS Binary CAM (BCAM) word circuit, a new ten-transistor CAM cell is also presented. Moreover, this thesis proposes a novel Quadruple CAM (QCAM) circuit design based on the static pseudo-CMOS logic structure to provide a more flexible solution than the conventional Ternary CAM (TCAM).

The whole design was fabricated with the TSMC 0.35 μm single-poly quadruple-metal (SPQM) CMOS process. With a 128 words by 30 bits BCAM size, the measurement results indicate that the proposed circuit works up to 85 MHz (include I/O pad delay) with the power consumption of 23 mW at 3.3 V supply voltage. Furthermore, by the low voltage measurement results, the proposed circuit works up to 32 MHz at 1.5 V supply voltage. Moreover, with a 128 words by 30 bits QCAM size, the measurement results indicate that the proposed circuit works up to 71 MHz with the power consumption of 29 mW at 3.3 V supply voltage, and 15 MHz at 1.4 V.

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