本論文主要針對類比數位轉換器(ADC)電路開發內建自我測試(BIST)方法並且進一步分析與設計ADC電路之內建自我測試電路。
在測試信號產生器電路設計方面，本論文提出一種以震盪器(Oscillator)為基礎之可重建式(Reconfigurable)正弦波產生器電路。其原理便是將一個可重建式調變器(Modulator)操作在不同的模式(Mode)以產生不同頻率範圍的正弦波測試信號以及此信號之數位參考(Reference)信號。因此不需要額外的電路便能產生直接比對之ADC BIST架構中所需要的參考樣本(Pattern)。此外，所產生之測試信號相對於純粹利用類比信號產生器而言更能精確控制。將此提出之信號產生器所產生的測試信號應用到一個六位元管線式(Pipelined)ADC所得到之測試結果與在理想測試信號下的測試結果在頻譜分析(Spectral analysis)下比較，也得到一致的測試結果。
在輸出響應分析部份，本論文提出一種「改良式ADC正弦波直方圖測試方法」(Modified ADC sine-wave histogram testing method)，藉由分析ADC電路在正弦波直方圖測試方法下所得到的靜態參數(Static parameter)之結果來預估ADC電路「信號雜訊比(SNR)之減少(Degradation)量」。相較於傳統上欲完整驗證ADC電路之整體效能，不但需要執行直方圖分析還需要執行快速傅立葉轉換(Fast Fourier Transform, FFT)之頻譜分析才能得到動態參數的資訊，所提出之方法能夠更加有效並降低成本。基於此提出之測試方法，利用座標軸旋轉數位計算器 (Coordinate Rotation Digital Computer, CORDIC)演算法去設計供參考用的弦波直方圖(Sine-wave histogram)計算器及估算ADC電路之效能的計算電路來實現一種ADC電路之輸出響應分析(Output response analyzer, ORA)電路。所開發之輸出響應分析電路使用0.18-m 製程技術合成，並且將其實際應用於一個商用8位元ADC(AD 7822)的量測，來對所開發之電路進行完整的驗證。

In this dissertation, we develop an effective built-in self-test (BIST) structure and design the corresponding BIST circuit for analog-to-digital converters (ADCs).
In the analysis and design of test stimulus generator circuit for ADC BIST, an oscillator-based reconfigurable sinusoidal signal generator is proposed. The concept of this proposed stimulus generator is to reconfigure the modulator into different operation mode to generate the test stimulus which has a wide range of frequency. In addition, not only the test stimulus but also the digital reference signal can be generated concurrently. Therefore, a direct comparison-based ADC BIST structure can be perform to compare the ADC output code and the concurrently generated digital reference pattern without extra area overhead. Compared with pure analog sinusoidal test stimulus generator, the generated signal’s quantities can be precisely controlled. A practical ADC BIST for a 6-bit pipelined ADC is designed by using the proposed oscillator-based reconfigurable sinusoidal signal generator as the excitation generator. The simulations of the testing results, by applying the generated stimulus, shows a good agreement to the testing result with ideal stimulus in the spectrum analysis.
In the development of output response analyzer (ORA) for ADC BIST, a modified sine-wave histogram testing method for ADCs is proposed. This method analyzes the relationships between the estimated degradation of the SNR value and the test results obtained by using the sine-wave histogram test. Conventionally, not only the analysis of histograms but also the spectral analyses have to be carried out to get the information of the overall parameters. The modified ADC sine-wave histogram testing method can be more effective and lower costs. An ADC ORA circuit, using the COordinate Rotation Digital Computer (CORDIC) technique, is analyzed and designed based on the proposed modified test method. The CORDIC technique is used to not only realize a reference sine-wave histogram calculator but also perform an ADC parameter evaluator. The developed ORA circuit is synthesized in a 0.18-m technology and applied to an 8-bit commercial ADC, AD 7822, to verify our designs.

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