簡易檢索 / 詳目顯示

回結果列表
研究生： 陳泱儒
Chen, Yang-Ru
論文名稱： 共用放大器與放寬回授路徑時間之三階雙重取樣三角積分調變器
An Operational Amplifier Sharing in Double-Sampled 3rd-Order Sigma-Delta Modulator with Relaxed Feedback Path Timing
指導教授： 劉濱達
Liu, Bin-Da
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2013
畢業學年度： 101
語文別： 英文
論文頁數： 79
中文關鍵詞： 放寬回授路徑時間技術 、運算放大器共用技術 、雙倍取樣技術 、逐漸趨近式類比數位轉換器
外文關鍵詞： relaxed feedback path timing, opamp-sharing technique, double-sampling, SAR ADC
相關次數： 點閱：126  下載：0 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

    • 本論文提出一種應用於無線通訊系統之雙倍取樣三角積分調變器，在使用雙倍取樣和共用放大器兩項技術的情況下，將取樣頻率變為兩倍並保持低功率消耗的特性。本架構中，放寬了調變器回授路徑的處理時間，使得量化器能以低功率效耗的逐漸趨近式類比數位轉換器來實現，降低整體的功率消耗。在加法器的設計上，將取樣電容共用，改善了路徑過多的缺點，藉此降低電路需求，此外也讓加法器運作時間縮短，降低功率消耗。
    本電路使用90 nm一層多晶矽九層金屬線製程，設計出在供應電壓1.2 V、取樣頻率80 MHz、超取樣率16倍的設定下，訊號頻寬為2.5 MHz的三階雙倍取樣之三角積分調變器。由模擬結果得知，訊雜比為78.58 dB，有效位元數為12.76位元，整體功率消耗為3.5 mW，FoM為101 fJ/ conversion。

    This thesis presents the proposed double-sampled sigma-delta modulator which is designed for the application in wireless communication system. With the techniques of double-sampling and operational amplifier sharing, the sampling frequency is doubled while the power consumption is maintained. The SAR ADC is implemented as quantizer to reduce the power consumption, because the relaxed feedback timing is enough for conversion time of SAR ADC. Besides, the sampling capacitors are shared in the adder to improve the feedback factor and the adder is only active for short time. Therefore, the requirement and power consumption for the adder can be reduced.
    The proposed double-sampled third-order sigma-delta modulator is simulated in 90-nm 1P9M 1.2-V CMOS process technology. The sampling frequency of circuit is 80 MHz and the signal bandwidth is 2.5 MHz with a supply voltage of 1.2 V. Simulation results show that the 78.58-dB SNDR and 12.76-bit resolution are achieved under 16-X oversampling ratio. The total power consumption is 3.5 mW while FOM is 101 fJ/conversion.

    Abstract (Chinese) i Abstract (English) iii Acknowledgement v Table of Contents vii List of Tables ix List of Figures x Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Organization of the Thesis 2 Chapter 2 Fundamental of Analog-to-Digital Converter 5 2.1 Introduction of Analog-to-Digital Converter 5 2.1.1 Nyquist rate data converter 7 2.1.2 Oversampling data converter 8 2.2 Sigma-Delta Modulator 9 2.2.1 Oversampling technique 9 2.2.2 Noise-shaping technique 12 2.2.3 Multi-bit quantization topology 16 2.3 Successive Approximation Register ADC 17 Chapter 3 Proposed Sigma-Delta Modulation Structure 21 3.1 Low-Distortion ΣΔ ADC 22 3.2 Prior Art of Improved Low-Distortion Sigma-Delta Modulator 26 3.2.1 Relaxed feedback path timing 26 3.2.2 The noise-coupling enhancement technique 28 3.2.3 DAC capacitor resetting scheme 29 3.3 Proposed Low-Distortion Sigma-Delta Modulator 30 3.3.1 Proposed architecture 31 3.3.2 Timing diagram 33 3.3.3 Matlab simulation 34 Chapter 4 Implementation in Circuit Level 43 4.1 Loop Filter Design 44 4.1.1 Switched-capacitor integrator 44 4.1.2 Opamp design 47 4.2 Implementation of Quantizer 51 4.3 DWA and DAC circuits 56 4.4 Clock Generator 59 4.5 Simulation Results 62 4.6 Microphotograph and Measurement Environment 66 Chapter 5 Conclusions and Future Work 69 5.1 Conclusions 69 5.2 Future Work 70 References 73 Biography 79

    [1] D. Johns and K. W. Martin, Analog Integrated Circuit Design. New York: John Wiley & Sons, 1997, pp. 373–390.
    [2] R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters. New York: IEEE Press, 2005, pp. 1–40.
    [3] P. Rombouts, J. D. Maeyer and L. Weyten, “A 250-kHz 94-dB double-sampling modulation A/D converter with a modified noise transfer function,” IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 1657–1662, Oct. 2003.
    [4] B. Razavi, Design of Analog Cmos Integrated Circuits. Boston, MA: McGraw-Hill, 2001, pp. 201–345.
    [5] W. Sansen, Analog Design Essentials. Dordrecht, Netherlands: Springer, 2006, pp. 603–677.
    [6] R. Schreier, “An empirical study of high-order single-bit delta-sigma modulators,” IEEE Trans. Circuits Syst. II, Analog Digit. Process., vol. 40, pp. 461–466, Aug. 1993.
    [7] R. T. Baird and T. S. Frez, “Improved delta-sigma DAC linearity using data weighted averaging,” in Proc. Int. Symp. Circuits and Syst., pp. 13–16, May 1995.
    [8] S. N. Mohammad and G. C. Temes, “A high-resolution multibit sigma-delta ADC with digital correction and relaxed amplifier requirements,” IEEE J. Solid-State Circuits, vol. 28, pp. 648–660, Apr. 1993.
    [9] Q.-Q. Wang, B.-J. Ge, X.-X. Feng and X.-A. Wang, “Digital noise shaping multibit delta-sigma modulator,” Electron. Lett., vol. 46 , pp. 1110–1111, Aug. 2010.
    [10] N. Maghari, S. Kwon, and U. K. Moon, “74 dB SNDR multi-loop sturdy-MASH delta-sigma modulator using 35 dB open-loop opamp gain,” IEEE J. Solid-State Circuits, vol. 44, pp. 2212–2221, Aug. 2009.
    [11] R. Schreier, J. Silva, J. Steensgaard, and G. C. Temes, “Design-oriented estimation of thermal noise in switched-capacitor circuits,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, pp. 2358–2368, Nov. 2005.
    [12] J. Silva, U. Moon, J. Steensgaard, and G. C. Temes, “Wideband low-distortion delta–sigma ADC topology,” Electron. Lett., vol. 37 , pp. 737–738, Jun. 2001.
    [13] K. Lee and G. C. Temes, “Improved low-distortion ΔΣ ADC topology,” Electron Lett., vol. 45, pp. 730–731, Jul. 2009.
    [14] A. Gharbiya and D. A. Johns, “On the implementation of input feed-forward delta-sigma modulators,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, pp. 453–457, Jun. 2006.
    [15] W. Shen and G. C. Temes, “Double-sampled ΔΣ modulator with relaxed feedback timing,” Electron. Lett., vol. 45, pp. 875–877, Aug. 2009.
    [16] Y. Nishida, K. Hamashita, and G. C. Temes, “An enhanced dual-path ΔΣ A/D converter,” IEICE Trans. Electron., vol. E93-C, pp. 884–892, Jun. 2010.
    [17] I. J. Chao, C. L. Hsu, B. D. Liu, C. Y. Huang, and S. J. Chang, “Behavior model for comparator-based switched-capacitor SDM with relaxed DEM timing,” in Proc. IEEE Int. Conf. Green Circuits and Syst., pp. 495–498, Jun. 2010.
    [18] C. H. Kuo, D. Y. Shi, and K. S. Kim, “A low-voltage four-order cascade delta-sigma modulator in 0.18-μm CMOS,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, pp. 2450–2461, Sep. 2010.
    [19] Y. C. Huang and T. C. Lee, ”A 10-bit 100-MS/s 4.5-mW pipelined ADC with a time-sharing technique,” IEEE Trans. Circuits Syst. I, Reg. Papers, pp. 1157–1166, Jun. 2011.
    [20] I. J. Chao, W. C. Chen, C. M. Kuo, B. D. Liu, H. W. Ting, S. J. Chang and C. Y. Huang, “A low-distortion relaxed-DEM-timing delta-sigma modulator without extra adder in the quantizer input,” in Proc. 22nd VLSI Design/CAD Symp., pp. 480–483, Aug. 2011.
    [21] L. Liu, D. Li, L. Chen, Y. Ye, and Z. Wang, “A 1-V 15-bit audio ΔΣ-ADC in 0.18µm CMOS,” IEEE Trans. Circuits Syst. I, Reg. Papers, pp. 915–¬¬925, May 2012.
    [22] S. Lee, J. Chae, M. Aniya, S. Takeuchi, P. K. Hanumolu, and G. C. Temes, “A double-sampled low-distortion cascade ΔΣ modulator adder/integrator for WLAN application,” in Proc. IEEE Cust. Integr. Circuits Conf., pp. 1–¬¬4, Sep. 2011.
    [23] K. Y. Tiew and M. Je, “A 0.06-mm2 double-sampling single-OTA 2nd-order ΔΣ modulator in 0.18-μm CMOS technology,” in Proc. IEEE Asian Solid-State Circuits Conf., pp. 253–¬¬256, ¬¬Nov. 2011.
    [24] O. Rajaee, S.Takeuchi, M. Aniya, K. Hamashita and U. Moon, "Low-OSR over-ranging hybrid ADC incorporating noise-shaped two-step quantizer", IEEE J. Solid-State Circuits, vol. 46, no. 11, pp. 2458–¬¬2468, Nov. 2011.
    [25] K. Lee, G. C. Temes, and F. Maloberti, "Noise-coupled multi-Cell delta-sigma ADCs," in Proc. IEEE Int. Symp. Circuits and Syst., pp. 249–¬¬252, May 2007.
    [26] Y. Wang and G. C. Temes, "Noise-coupled continuous-time delta-sigma ADCs," Electron. Lett., vol. 45, pp. 302–¬¬303, Mar. 2009.
    [27] V. Hariprasath, J. Guerber, S.-H. Lee, U. Moon, "Merged capacitor switching based SAR ADC with highest switching energy efficiency," Electron. Lett., vol.46, pp. 620–621, Apr. 2010.
    [28] J. Chae, S. Lee, M. Aniya, S. Takeuchi, P. K. Hanumolu, and G. C. Temes, “A 63 dB 16mW 20 MHz BW double-sampled ΔΣ analog-to-digital converter with an embedded-adder quantizer,” in Proc. IEEE Cust. Integr. Circuits Conf., pp.1–¬¬4, Sep. 2010.
    [29] M. Daliri, M. Maymandi-Nejad and K. Mafinezhad, “Distortion analysis of bootstrap switch using Volterra series,” IET Circuits, Devices and Syst., vol. 46, pp. 400–¬¬401, Dec. 2009.
    [30] Z. Yang, L. Yao, and Y. Lian, “A 0.5-V 35-μW 85-dB DR double-sampled ΔΣ modulator for audio applications,” IEEE J. Solid-State Circuits, pp. 722–¬¬735, Mar. 2011.
    [31] Y. L. Shen, “Design of a high-efficient delta-sigma modulator and simplified data weighted averaging algorithm, ” M.S. thesis, Dept. Elect. Eng., National Cheng Kung Univ., Tainan, Taiwan, R. O. C., 2012.
    [32] F. Michel, and M. S. J. Steyaert, “A 250 mV 7.5μW 61 dB SNDR SC ΔΣ modulator using near-threshold-biased inverter amplifier in 130 nm CMOS,” IEEE J. Solid-State Circuits, vol. 47, pp. 709–721, Mar. 2012.
    [33] L. Bos, G. Vandersteen, P. Rombouts, A. Geis, A. Morgado, Y. Rolain, G. V. Plas and J. Ryckaert, “Multirate cascaded discrete-time low-pass ΔΣ modulator for GSM/Bluetooth/UMTS,” IEEE J. Solid-State Circuits, vol. 45, pp. 1198–1208, Jun. 2010.
    [34] O. Rajaee, T. Musah, N. Maghari, S. Takeuchi, M. Aniya, K. Hamashita, and U. K. Moon, “Design of a 79 dB 80 MHz 8X-OSR hybrid delta-sigma/pipelined ADC,” IEEE J. Solid-State Circuits, vol. 45, pp. 719–730, Apr. 2010.
    [35] K. Yamamoto and A. C. Carusone, “A 1-1-1-1 MASH delta-sigma modulator with dynamic comparator-based OTAs,” IEEE J. Solid-State Circuits, vol. 47, pp. 1866–1883, Aug. 2012.
    [36] N. Maghari, and U. K. Moon, “A third-order DT ΔΣ modulator using noise-shaped bi-directional single-slope quantizer,” IEEE J. Solid-State Circuits, vol. 46, pp. 2882–2891, Dec. 2011.
    [37] A. P. Perez, E. Bonizzoni, and F. Maloberti, “A low-power third-order ΣΔ modulator using a single operational amplifier” in Proc. IEEE Int. Symp. Circuits and Syst., pp 1371–1374, May 2011.
    [38] C. C. Liu, S. J. Chang, G. Y. Huang, and Y. Z. Lin, “A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure,” IEEE J. Solid-State Circuits, vol. 45, pp. 731–740, Apr. 2010.
    [39] C. C. Liu, “Design of high-speed energy-efficient successive-approximation analog-to-digital converters, ” Ph.D. dissertation, Dept. Elect. Eng., National Cheng Kung Univ., Tainan, Taiwan, R. O. C., 2010.
    [40] J. K. Fiorenza, T. Sepke, C.G. Sodini, P. Holloway and H.-S. Lee, “Comparator-based switched-capacitor circuits for scaled CMOS technologies,” IEEE J. Solid-State Circuits, pp. 2658–2668, Dec. 2006.

    無法下載圖示 校內：2018-08-26公開
    校外：不公開
    電子論文尚未授權公開，紙本請查館藏目錄
    QR CODE