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研究生: 邱泰恩
Chiu, Tai-En
論文名稱: 可擴充式指令集之設計與其工具鏈實現
An extensible instruction set architecture design and its toolchain implementation
指導教授: 陳中和
Chen, Chung-Ho
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電腦與通信工程研究所
Institute of Computer & Communication Engineering
論文出版年: 2008
畢業學年度: 96
語文別: 英文
論文頁數: 54
中文關鍵詞: 可擴充式指令集工具串
外文關鍵詞: extensible ISA, porting, toolchain, binutils
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  • 現今嵌入式微處理器為了更有效率地處理不同類型的應用,而發展出 application specific instruction-set processor (ASIP) 的設計模式。這篇論文中我們提出了一個適用於ASIP 的可擴充式指令集架構設計。
    藉由刪減原有ARMv4 指令集架構中極少使用的功能與重組其位元編碼,產生一組未定義的延伸指令集空間,以供增加特殊需求的指令功能。我們並以此指令集架構為基礎,實做出互相搭配的軟體工具串,包括組譯器、連結器、及基本的函式庫。
    為了驗證所設計的指令集架構以及軟體工具串的正確性,我們修改一經由Linux 驗證過的RISC32 處理器,以模擬軟體搭配硬體描述語言的方式,將我們軟體工具產生的可執行檔讀入並執行,使其輸出結果與參照的結果互相比對,以確認其正確無誤。

    The design methodology of embedded processors can adapt to the design flow of Application-Specific Instruction-Set Processor (ASIP) to perform various types of operations more efficiently. In this thesis, we present a design of extensible instruction set architecture (ISA) for ASIP systems.
    By removing the less frequently used functionality of the ARMv4 ISA and rearranging its binary encoding, we obtain an extended instruction encoding space. This extended space can be added with special-purpose instructions without any constraint. To use this extensible ISA, we also implement the corresponding software toolchain that includes an assembler, a linker, and some basic libraries.
    To verify the software toolchain, we modify our RISC32 processor to perform verification. We first use our toolchain to generate an executable binary image, and then execute this image by an HDL simulator which is our RISC32 processor. At last, we compare the simulator’s output results with the referenced ones for correctness checking.

    Chapter 1 INTRODUCTION 1 1.1 Motivation 1 1.2 Thesis organization 2 Chapter 2 EXTENSIBLE ISA 3 2.1 Background 3 2.1.1 Basic ARM architecture and instruction set 3 2.1.2 ARMv4 ISA encoding principles 4 2.1.3 Addressing modes 7 2.2 Rearrange binary encoding 8 2.2.1 Encoding strategy 8 2.2.2 The leftover conditions 9 Chapter 3 BINARY UTILITY 13 3.1 GNU toolchain 13 3.2 GAS 15 3.2.1 GAS introduction 15 3.2.2 GAS internals 15 3.2.3 GAS backends support 18 3.3 Binary file descriptor library 22 3.3.1 BFD introduction 22 3.3.2 BFD structure 22 3.3.3 BFD relocation handling 23 3.3.4 BFD backends support 26 3.4 Linker 30 3.4.1 GNU linker 30 3.4.2 LD internals 31 Chapter 4 IMPLEMENTATION & VERIFICATION 33 4.1 Modification of CPU backend support 33 4.1.1 Opcode library 33 4.1.2 GAS backend 34 4.1.3 LD backend 35 4.1.4 Summary of modified files 36 4.2 Verification of the toolchain 38 4.3 New libraries 41 4.4 Hardware environment 44 4.5 Verification 45 4.5.1 Test suites 45 4.5.2 Result verification 47 Chapter 5 CONCLUSION 52 5.1 Conclusion 52 5.2 Future work 53

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    Computer and Communication Engineering, NCKU, June 2006.
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