本論文實現兩個架構應用於低功率消耗之系統的類比數位轉換器，其電路設計採用TSMC 0.18μm 1P6M製程實現之。第一個架構為單端輸入連續漸進式類比數位轉換器，採用PMOS與NMOS作為比較器的差動輸入級，以確保訊號的輸入範圍與供應電壓相同。此外，數位類比轉換器採用切換式電容電路的實現方式，以降低靜態消耗功率。此八位元轉換器所需供應電壓為1.8V，取樣頻率為每秒一百萬次與輸入頻率499.023千赫，其電路效能為訊號對雜訊與失真比為46.219 dB，積分非線性誤差與微分非線性誤差的範圍分別為-0.37 ~ 0.31 LSB與-0.37 ~ 0.51 LSB，整體功率消耗為273 μW，以及佈局面積(包含PAD)為780 μm × 780 μm。
第二個架構以全差動式連續漸進式類比數位轉換器實現。其中二級比較器不需參考偏壓源電路，以達到零靜態功率消耗。由差動電路架構的特性，降低雜訊影響進而增進電路的訊號雜訊比。十位元連續漸進式類比數位轉換器的效能於供應電壓1V、取樣頻率每秒一百萬次與輸入頻率149.4千赫，之訊號對雜訊與失真比為57.02 dB，積分非線性誤差與微分非線性誤差分別為-2.1 ~ 2.1 LSB與-1 ~2.2 LSB，整體功率消耗為22 μW，以及能量效率38 fJ/Conversion-step。

This thesis presents the two analog-to-digital converters for low-power system applications, and the circuit design is realized by using TSMC 0.18μm 1P6M process. The first architecture is a single-ended SAR-ADC, the PMOS and NMOS are adopted in the input differential stage of comparator to ensure the input signal range would be equal to the value of supply voltage. Besides, the realization of digital-to-analog converter is using switch-capacitor technique, which could reduce the static power dissipation. The result of 1.8V 1MS/s 8-bit SAR-ADC, shows the SNDR is 46.219 dB with 499.023 kHz input signal, INL and DNL is -0.37 ~ 0.31 LSB and -0.37 ~0.51 LSB, total power consumption is 273 μW, and the area of layout (including PAD) is 780 μm × 780 μm.
The second architecture is a fully-differential SAR-ADC. The modified two-stage comparator design except the bias circuit could reach the zero static power dissipation. Owing to the characteristic of differential circuit, it could reduce the noise effect to improve the SNR of circuits. The result of 1V 1MS/s 10-bit SAR-ADC, shows the SNDR is 57.02 dB by using the 149.4 kHz input signal, INL and DNL is -2.1 ~ 2.1 LSB and -1 ~2.2 LSB, total power consumption is 22 μW, and energy efficient is 38fJ/conversion-step.

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