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研究生：	鄭儒陽 Zheng, Ju-Yang
論文名稱：	經驗模態分解之矽智財設計 Design of The Silicon Intellectual Property for Empirical Mode Decomposition
指導教授：	陳培殷 Chen, Pei-Yin
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 資訊工程學系 Department of Computer Science and Information Engineering
論文出版年：	2013
畢業學年度：	101
語文別：	英文
論文頁數：	62
中文關鍵詞：	經驗模態分解、矽智財設計、超大型積體電路
外文關鍵詞：	Empirical mode decomposition, silicon intellectual property, VLSI
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黃鄂等人於1998年提出了經驗模態分解法(Empirical mode decomposition,EMD)。這是一種的訊號處理演算法，可有效處理非線性與非穩態的訊號。近年來EMD被廣泛應用於各個領域中，也由於即時性(Real-time)的需求，許多EMD的硬體電路搭載於可程式邏輯(Field programmable gate array, FPGA)上的設計也在過去兩年中陸續被提出。在這裡我們對EMD提出了一種高彈性超大型積體電路的矽智財設計。在這設計中，我們可透過選擇資料寬度、極值選取器、包絡線產生器、以及停止準則來產生相對應的EMD硬體電路，並使用於不同的應用之中。為了驗證這套設計，我們產生三種不同的電路來檢測，而這些電路100-MHz的時脈下也可正確工作。

Empirical mode decomposition (EMD) is a effective algorithm for nonlinear and non-stationary signal analysis proposed by Haung et al. in 1998. EMD has been widely used in many application and many field programmable gate array (FPGA) implementations of EMD have been developed. A flexible very-large-scale integration intellectual property for EMD has been proposed in the thesis. This algorithm can dynamically perform various precision, data length, extrema extractor, envelope generator and stopping criterion for the real-time requirements of various EMD applications. The algorithm has been verified with three examples running very well at 100-MHz clock frequency.

摘要. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 Overview of . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Motivation and Objective . . . . . . . . . . . . . . . . . . . . . . . . . 2
3 Organization of This Thesis . . . . . . . . . . . . . . . . . . . . . . . . 4
Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1 Empirical Mode Decomposition(END) . . . . . . . . . . . . . . . . . . 5
2 Extrema Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Parabolic Interpolation . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Comparator Array . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 Envelope Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Lagrange Interpolation . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 Hermite Spline Interpolation . . . . . . . . . . . . . . . . . . . . 18
3.3 Cubic Spline Interpolation . . . . . . . . . . . . . . . . . . . . . 22
4 Stopping Criterion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1 Standard Deviation . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2 K Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.3 Energy Difference Tracking Method . . . . . . . . . . . . . . . . 26
The Proposed Design for EMD . . . . . . . . . . . . . . . . . . . . . . . . . 27
1 System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2 Extrema Extractor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.1 Method I : Parabolic Interpolation . . . . . . . . . . . . . . . . 31
2.2 Method II : Comparator Array . . . . . . . . . . . . . . . . . . 33
3 Envelope Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4 Interpolation Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.1 Method I : Sawtooth Interpolation . . . . . . . . . . . . . . . . 37
4.2 Method II : Cubic Hermite Interpolation . . . . . . . . . . . . . 38
4.3 Method III : Cubic Spline Interpolation . . . . . . . . . . . . . . 39
5 Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6 Stopping Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1 EMD Verilog-IP Generator . . . . . . . . . . . . . . . . . . . . . . . . . 44
2 Software Develop for Generator . . . . . . . . . . . . . . . . . . . . . . 46
3 Verification and Simulation Result . . . . . . . . . . . . . . . . . . . . . 47
3.1 Method I : Verify with EDA Tools . . . . . . . . . . . . . . . . 47
3.2 Layout Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.3 Method II : Verify with FPGA . . . . . . . . . . . . . . . . . . 50
4 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5 Precision Issue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6 Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.1 Result - Design 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.2 Result - Design 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.3 Result - Design 3 . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Conclusions and Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . 59
1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
                                    

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校內：2023-12-31公開
校外：不公開電子論文尚未授權公開，紙本請查館藏目錄

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