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| 研究生： |
林佩玉 Lin, Pei-Yu |
|---|---|
| 論文名稱： |
單一基板整合氮化鋁鎵/氮化鎵高電子遷移率電晶體之直接耦合場效邏輯（DCFL）與互補邏輯（CMOS）電路的開發 Development of Monolithically Integrated AlGaN/GaN HEMTs-Based DCFL and CMOS Logic Circuits |
| 指導教授： |
王永和
Wang, Yeong-Her |
| 學位類別： |
碩士 Master |
| 系所名稱： |
電機資訊學院 - 微電子工程研究所 Institute of Microelectronics |
| 論文出版年： | 2025 |
| 畢業學年度： | 113 |
| 語文別： | 英文 |
| 論文頁數： | 144 |
| 中文關鍵詞： | 氮化鋁鎵/氮化鎵高電子遷移率電晶體 、直接耦合場效應電晶體 、氮化鎵互補邏輯電路 、單一基板整合 、表面處理 、氧化層 |
| 外文關鍵詞： | AlGaN/GaN HEMTs, Direct-Coupled FET Logic, GaN Complementary Logic Circuits, Monolithic Integration, Surface Treatment, Oxide Layer |
| 相關次數： | 點閱：51 下載：0 |
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本研究的核心在於充分利用氮化鋁鎵/氮化鎵高電子遷移率電晶體的優越特性，設計並實現單一基板整合的直接耦合場效應電晶體邏輯架構（DCFL）和氮化鎵互補邏輯電路（GaN CMOS）。此設計旨在解決傳統分立式元件設計中因封裝與布線所導致的寄生電感問題，進而顯著提升高頻操作下的性能與穩定性。
在研究的第一部分，我們利用經過閘極蝕刻處理的耗盡型（D-mode）與增強型（E-mode）AlGaN/GaN HEMTs，將其集成於單一晶片，實現高性能的DCFL反相器。為了改善元件界面特性，採用了TMAH溶液表面處理以及沉積氧化層後進行 500℃ 15分鐘的氮氣退火，成功減少界面陷阱，大幅提升元件性能。在5V供電電壓下，DCFL反相器實現了4.66V的輸出邏輯擺幅、2.01V的低邏輯噪聲容限、1.7V的高邏輯噪聲容限以及23.43 V/V的高電壓增益，展現出優異的抗干擾能力與穩定性。
第二部分中，我們進一步針對p通道和n通道HEMTs進行精密的閘極蝕刻處理，成功實現增強型操作，構建了單一基板整合的GaN互補邏輯電路。其中，n通道與p通道的閾值電壓分別為0.5V和-0.5V。在2V供電電壓下，實驗結果顯示氮化鎵互補邏輯電路實現了1.949V的輸出邏輯擺幅、0.3789V的低邏輯噪聲容限、1.31V的高邏輯噪聲容限、0.26V的過渡窗口以及12.8 V/V的高電壓增益。
本研究展現了AlGaN/GaN HEMTs在高頻與高效邏輯電路設計中的巨大潛力，成功開發出具優異性能的DCFL反相器與GaN CMOS邏輯電路，為高頻應用提供了全新的方向，並為下一代高效能電子系統的開發奠定了堅實基礎。
This thesis focuses on leveraging the exceptional properties of AlGaN/GaN high-electron-mobility transistors (HEMTs) to design and implement direct-coupled FET logic (DCFL) and GaN complementary logic circuits (GaN CMOS) on a single substrate. The proposed design aims to address the parasitic inductance issues inherent in traditional discrete component designs due to packaging and interconnection, thereby significantly enhancing performance and stability under high-frequency operations.
In the first part of the study, depletion-mode (D-mode) and enhancement-mode (E-mode) AlGaN/GaN HEMTs were integrated on a single chip to realize a high-performance DCFL inverter. To improve the device interface characteristics, TMAH surface treatment and post-deposition annealing of the oxide layer at 500°C for 15 minutes in a nitrogen environment were employed, effectively reducing interface traps and significantly enhancing device performance. Under a 5V supply voltage, the DCFL inverter achieved an output voltage swing of 4.66V, a low-level noise margin (NML) of 2.01V, a high-level noise margin (NMH) of 1.7V, and a voltage gain of 23.43 V/V, demonstrating excellent noise immunity and stability.
In the second part, precise gate etching techniques were applied to p-channel and n-channel HEMTs to successfully achieve enhancement-mode operation, culminating in the development of GaN complementary logic circuits integrated on a single substrate. The threshold voltages (VTH) of the n-channel and p-channel devices were 0.5V and -0.5V, respectively. Experimental results under a 2V supply voltage revealed that the GaN CMOS logic circuit achieved an output voltage swing of 1.949V, an NML of 0.3789V, an NMH of 1.31V, a transition window of 0.26V, and a voltage gain of 12.8 V/V.
This study highlights the immense potential of AlGaN/GaN HEMTs in high-frequency and high-efficiency logic circuit design, successfully developing high-performance DCFL inverters and GaN CMOS logic circuits. These advancements offer new directions for high-frequency applications and lay a solid foundation for developing next-generation high-performance electronic systems.
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校內：2030-02-05公開校外：2030-02-05公開