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研究生：	陳雅婷 Chen, Ya-Ting
論文名稱：	應變記憶技術改善奈米尺寸互補式金氧半場效電晶體的特性以及其幾何效應的研究 Investigation on the Performance Improvement and Geometric Effects of Nanoscale CMOS Devices with SMT (Stress Memorization Technique)
指導教授：	張守進 Chang, Shoou-Jinn 吳三連 Wu, San-Lein
學位類別：	碩士 Master
系所名稱：	理學院 - 光電科學與工程研究所 Institute of Electro-Optical Science and Engineering
論文出版年：	2009
畢業學年度：	97
語文別：	英文
論文頁數：	69
中文關鍵詞：	應變記憶技術
外文關鍵詞：	stress memorization technique
相關次數：	點閱：140 下載：2
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在本論文中，最佳化的低成本應變記憶技術 (SMT) 已經應用在40奈米的製程技術上，並且有改善互補式金氧半場效電晶體特性的能力。其中我們將元件成長在(100)晶格方向的基板，且通道方向也為<100>，這樣應變記憶技術 (SMT) 對於N 型金氧半場效電晶體仍然有提升8%的驅動電流的能力，同時又不會對P 型金氧半場效電晶體有任何的影響，例如降低載子遷移率和硼擴散效應等等，如此就不需要額外蝕刻製程去控制應變記憶技術對P 型金氧元件的退化。另外為了進一步探討應變記憶技術的應力儲存機制，以及應力傳導的模型，藉由改變不同的幾何結構去對應其元件特性變化，是非常有效的方法。我們發現到在越小的閘極距離 (poly spacing) 與越短的源極(汲極)擴散長度 (source drain diffusion length)，其應變記憶技術改善N 型金氧元件的能力變差，也就是說應變記憶技術的應力貢獻主要是由源極(汲極)擴散區域所提供的，而不是大部分文獻提出由閘極主導的機制。

Implementation of strained-Si MOSFETs with optimum low cost stress-memorization technique for 40nm technology CMOS process was demonstrated. Devices fabricated on (100) substrate with <100> channel orientation provides additional 8% current drivability improvement for strained-Si nMOSFETs without any degradation of pMOSFETs performance. The SMT mechanism was experimentally verified by studying the impact of layout geometry (length of source/drain LS/D, poly spacing LP/P, and gate width W) on the device performance. The SMT devices with LS/D down to 0.11 μm and poly space reduced to 120 nm, no obvious current improvement and more performance degradation is observed compared with control device, indicating that the benefit of stress-memorization technique is substantially eliminated and showing that the SMT-induced stress is originated from the source/drain region in our case.

Abstract (Chinese)                                                    Ⅰ
Abstract (English)                                                Ⅱ
Contents                                                       IV
Table Captions                                           VII
Figure Captions                                                        VIII
Chapter 1 Introduction                                   1
1 General Background                                   1
2 Motivation                                           2
3 Organization                                         2
Chapter 2 Properties of Stress Memorization Technique    4
1 Physics of Strain Effects in CMOS Transistors        4
2 Mechanism of Strain Memorization                     5
3 Types of SMT Stress Model                            7
3.1 Poly Gate Stress Model                             7
3.2 Source-Drain Stress Model                          7
Chapter 3 Device Fabrication and Measurement Setup      14
1 Device Fabrication                                  14
1.1 Process Flow                                      14
1.2 Geometric Structure Parameters                    16
2 Measurement System                                  16
Chapter 4 Stress Memorization Effects on CMOS           18
1 Basic Electrical Characteristics of pMOSFETs        19
1.1 Channel Orientation and Stress Control            19
1.2 Suppression of Boron Penetration                  20
1.3 C–V Measurement                                  20
1.4 I–V Measurement                                  20
2 Basic Electrical Characteristics of nMOSFETs        22
2.1 I–V Measurement                                  22
2.2 Strain Benefits over Varied Gate Length           23
Chapter 5 Geometric Dependence of nMOSFETs with 
          morization Technique                          36
1 Impact of Poly Spacing Shrinks on NMOS              37
1.1 Test Structure and Parameters                     37
1.2 Results and Discussion                            37
2 Active Length Effects on NMOS                       38
2.1 Test Structure and Parameters                     39
2.2 Results and Discussion                            39
3 Gate Width Effects on NMOS                          40
3.1 Test Structure and Parameters                     40
3.2 Results and Discussion                            40
Chapter 6 Conclusions and Future Work                   60
1 Conclusions                                         60
2 Future Work                                         60
References                                              62
                                    

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2012-07-03公開

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