本論文研製毫米波CMOS次諧波降頻混頻器與低相位變化之可變增益放大器。整合壓控振盪器之60-GHz CMOS次諧波降頻混頻器採用TSMC CMOS 90-nm製程，混頻器主要以串接LO之bottom-LO架構，再加上被動及主動平衡器、緩衝放大器及並聯λ/4開路傳輸線。24-GHz及60-GHz低相位變化之可變增益放大器分別採用TSMC CMOS 0.18 μm及90 nm製程。24-GHz CMOS低相位變化之可變增益放大器，改變疊接架構放大器之等效輸出阻抗及轉導值，並使用基極浮接技術達到相位的平坦；而24-GHz CMOS線性增益調控及低相位變化之可變增益放大器，改變疊接架構放大器之等效輸出阻抗及回授之回授量，基極浮接技術及可變電容達到相位補償；60-GHz CMOS低相位變化之可變增益放大器，串接兩級增益控制級，利用兩級不同趨勢之頻率響應，達到相位補償。晶片皆採用fully on-wafer的量測方式。

This thesis presents the design of a 60-GHz millimeter-wave CMOS sub-harmonic mixer and 24-/60-GHz low-phase-variation variable gain amplifiers (VGAs). The designed RFICs are fabricated with TSMC CMOS 90 nm and TSMC CMOS 0.18 μm standard process, rerspectively. The 60-GHz CMOS sub-harmonic mixer with integrated VCO is mainly composed of the leveled-bottom-LO structure, passive and active baluns, and buffer amplifier. The first design of VGA is a 24-GHz CMOS low-phase-variation variable gain amplifier which uses the equivalent output impedance and transconductance (gm) by changing the cascode amplifier structure. The second 24-GHz VGA with a low-phase-variation and linear-in-dB gain control range is achieved with the adjusted equivalent output impedance and amount of feedback by changing cascode amplifier structure. The body-floating technique is also used to reduce phase variation versus gain control in the above VGA design. The 60-GHz VGA design cascades two gain control stages with different phase-change tendency to achieve the low phase variation.

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