在奈米金氧半元件淺溝槽隔離(STI)製造中, 高密度電漿化學沉積(HDP CVD)方式成功地提供了有效的解決方案。 然而，隨著元件不斷的微縮以提高元件特性的過程中, 傳統HDP沈積製程，在90nm以下會產生過多的溝槽空洞(void)而導致晶園良率損失。 為了克服這個傳統製程容易產生溝槽孔洞的問題, 吾人研發加入一道以NF3為基礎的乾式蝕刻, 再配合反覆式的沈積和蝕刻的新型STI製程。
本文報導利用這一種新型技術實怍的STI結構及電性分析究。 結構分析主要在探討如何調整最佳化製程參數, 如D/S(deposition/sputter)值與蝕刻厚度, 以及控制交替式沈積和蝕刻組合, 並觀察STI Divot 和 Step-height會對元件產生的影響。 在電性分析中, 則比較其漏電流及崩潰電壓的表現。 經由分析結果證實吾人所研發的新型製作技術更適合65nm以下金氧半電晶體元件的淺溝槽隔離的製作。

High density plasma chemical vapor deposition (HDP-CVD) has been successfully applied in the nano CMOS technology for shallow trench isolation (STI) gap fill. However, as CMOS device continue to shrink for improving its performance, the traditional HDP process can not meet the requirement of void free in STI gap-fill.
In this work, we propose a novel HDP gap-fill process to overcome the void issue for 65nm and beyond application. The novel HDP process was developed by joining an extra NF3-base dry etching in the traditional HDP process and to repeat the deposition and etch cycles. We investigated the key aspects of the novel STI process with both structure and electric analyses to provide better understanding on gap fill optimization and manufacturing capability.
In the structure analysis, we studied the influence of D/S(deposition/sputter) ratio and the etched thickness. Besides, impact of the deposition and etch cycles repeat rates, divot ad step-height on STI characteristics were realized. In the electrical analysis, the junction leakage and breakdown voltage were measured and compared to the traditional HDP process. Both analyses evidence the developed method is more suitable for 65nm and beyond CMOS technologies applications.

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