半導體的發展在幾十年來遵循摩爾定律下不斷提高電路密度，製程上的微縮(more Moore)越來越困難；所以業界朝另一條more than Moore路線發展，以達到異質整合及3D堆疊的目的，其中矽貫孔(Through Silicon Via, TSV)是能使晶片與晶片垂直連接的關鍵技術，利用導孔內金屬的垂直相連，可以達到尺寸縮小、3D堆疊及異質整合的目的。然而TSV技術也面臨到因材料間熱膨脹係數所產生的挑戰，在高溫TSV製程下，由於不同材料的熱膨脹係數不匹配而產生熱應力，從而發生TSV銅凸與脫層等結構問題。從過去的研究可以發現除了結構問題，也有熱應力對矽晶格產生的壓阻效應，使載子移動率上升而使元件失效形成排除區(Keep Out Zone, KOZ)，影響元件之性能及可靠度。
本研究主要目的為了解TSV各參數因子在熱製程下對應力分佈及載子移動率影響。透過有限元素法，對TSV進行模擬並分別計算其對n-MOS與p-MOS的影響。本研究藉由調整TSV直徑、深寬比、間距直徑比、排列角度幾何尺寸及製程溫度來模擬不同條件之下的應力，通過壓阻效應公式，計算並分析MOS於矽晶格方向[100]與[110]時，其載子移動率的變化趨勢與排除區的範圍變化。最後透過田口方法進行數據及變異分析，探討不同因子對載子移動率之影響程度，並對陣列式TSV提出優化設計，使載子移動率最大值減少約16~26%，以縮小排除區影響範圍，使晶片使用面積增加、尺寸更輕薄短小。

The development of semiconductors has followed Moore's law for decades to increase the circuit density. The process of more Moore is becoming more challenging. Therefore, moving towards more than Moore is an alternative for which through silicon via (TSV) is a key technology to directly connect wafers together vertically, enabling heterogeneous integration by 3D stacking. By utilizing vertically connected metal vias, the package size can be reduced while the device function can be improved. However, because of mismatch of the coefficients of thermal expansion (CTE) among the TSV materials, reliability issues such as delamination could occur due to thermal stresses at high temperature. Moreover, thermal stresses could induce piezoresistive effect on the silicon lattice and affect carrier mobilities which restrict the densification of TSVs in terms of keep-out-zones (KOZs), in addition to reliability concerns..
The main objective of this study is to reveal the effect of TSV parameters on stress distribution and carrier mobility under thermal strains by finite element numerical simulations via Taguchi method for [100] and [110] n-MOS and p-MOS semiconductors. The parameters investigated are the TSV diameter, TSV depth-to-width ratio, TSV pitch-to-diameter ratio, arrangement angle, and process temperature.
The results show that the array angle is the most influential factor, followed by the temperature, while the depth the least. Through optimization by Taguchi method, the maximum carrier mobility values of [100]p-MOS, [100]n-MOS, [110]n-MOS, and [110]p-MOS are reduced by 18.54%, 16.75%, 21.7%, and 26.52%, respectively, allowing better utilization of wafer area.

[1] C. A. Mack, Fifty years of Moore's law, IEEE Transactions on semiconductor manufacturing, vol. 24, no. 2, pp. 202-207 (2011).
[2] YOLE Roadmap, "Status of the Advanced Packaging Industry 2018-Advanced Package Roadmap," (2018).
[3] Semiwiki, "Semiconductor Packaging History and Primer," (2023).
[4] J. U. Knickerbocker, P. S. Andry,L. P. Buchwalter, A. Deutsch; R. R. Horton, K. A. Jenkins Y. H. Kwark, G. McVicker, C. S. Patel, R. J. Polastre, C. D. Schuster, A. Sharma, S. M. Sri-Jayantha, C. W. Surovic, C. K. Tsang, B. C. Webb, S. L. Wright, S. R. McKnight, E. J. Sprogis, B. Dang "Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection," IBM Journal of Research and Development, vol. 49, no. 4.5, pp.725-753 (2005).
[5] J. F. Croix, Cell and interconnect timing analysis using waveforms. ProQuest Dissertations Publishing (2002).
[6] Wikipedia, "Intel 8008".
[7] Wikipedia, "Dual in-line package".
[8] "TEXAS INSTRUMENTS."
[9] "XJTAG Development System."
[10] F. P. Carson, Y. C. Kim, and I. S. Yoon, "3-D stacked package technology and trends," Proceedings of the IEEE, vol. 97, no. 1, pp. 31-42 (2009).
[11] M. S. Bakir and J. D. Meindl, Integrated interconnect technologies for 3D nanoelectronic systems. Artech House (2008).
[12] J. U. Knickerbocker, P. S. Andry, B. Dang, R. R. Horton, M. J. Interrante, C. S. Patel, R. J. Polastre, K. Sakuma, R. Sirdeshmukh, E. J. Sprogis, S. M. Sri-Jayantha, A. M. Stephens, A. W. Topol, C. K. Tsang, B. C. Webb, S. L. Wright "Three-dimensional silicon integration," IBM Journal of Research and Development, vol. 52, no. 6, pp. 553-569 (2008).
[13] R. Fontaine, "World's First 3-layer Stacked CIS" Techinsights (2017).
[14] C. S. Selvanayagam, J. H. Lau, X. Zhang, S. Seah, K. Vaidyanathan, and T. Chai, "Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps," IEEE transactions on advanced packaging, vol. 32, no. 4, pp. 720-728 (2009).
[15] L. Jiang, Y. Liu, L. Duan, Y. Xie, and Q. Xu, "Modeling TSV open defects in 3D-stacked DRAM," in 2010 IEEE International Test Conference Austin, TX, USA, pp. 1-9 (2010).
[16] S. E. Thompson, G. Sun, Y. S. Choi, and T. Nishida, "Uniaxial-process-induced strained-Si: Extending the CMOS roadmap," IEEE Transactions on electron Devices, vol. 53, no. 5, pp. 1010-1020 (2006).
[17] A. P. Karmarkar, X. Xu, and V. Moroz, "Performanace and reliability analysis of 3D-integration structures employing through silicon via (TSV)," in 2009 IEEE International Reliability Physics Symposium, pp. 682-687 (2009).
[18] M. Moore, "International roadmap for devices and systems," Accessed: Jan,2021.
[19] N. Tanaka, T. Sato, Y. Yamaji, T. Morifuji, M. Umemoto, and K. Takahashi, "Mechanical effects of copper through-vias in a 3D die-stacked module," in 52nd Electronic Components and Technology Conference 2002.(Cat. No. 02CH37345), pp. 473-479 (2002).
[20] R.G. Filippi, J.F. McGrath, T.M. Shaw, C.E. Murray, H.S. Rathore, P.S. McLaughlin, V. McGahay, L. Nicholson, P.-C. Wang',J.R. Lloyd, M. Lane, R. Rosenberg, X. Liu, Y:Y. Wang, W. Landers, T. Spooner, J.J. Demarest, B.H. Engel, J. Gill, G. Goth "Thermal cycle reliability of stacked via structures with copper metallization and an organic low-k dielectric," in 2004 IEEE International Reliability Physics Symposium. Proceedings, pp. 61-67 (2004).
[21] J. Zhang, M. O. Bloomfield, J.-Q. Lu, R. J. Gutmann, and T. S. Cale, "Thermal stresses in 3D IC inter-wafer interconnects," Microelectronic Engineering, vol. 82, no. 3-4, pp. 534-547 (2005).
[22] P. Dixit, S. Yaofeng, J. Miao, J. H. Pang, R. Chatterjee, and R. R. Tummala, "Numerical and experimental investigation of thermomechanical deformation in high-aspect-ratio electroplated through-silicon vias," Journal of the Electrochemical Society, vol. 155, no. 12, p. H981 (2008).
[23] N. Ranganathan, K. Prasad, N. Balasubramanian, and K. Pey, "A study of thermo-mechanical stress and its impact on through-silicon vias," Journal of micromechanics and microengineering, vol. 18, no. 7, p. 075018 (2008).
[24] X. Liu, Q. Chen, P. Dixit, R. Chatterjee, R. R. Tummala, and S. K. Sitaraman, "Failure mechanisms and optimum design for electroplated copper through-silicon vias (TSV)," in 2009 59th Electronic Components and Technology Conference, pp. 624-629 (2009).
[25] K. H. Lu, X. Zhang, S.-K. Ryu, J. Im, R. Huang, and P. S. Ho, "Thermo-mechanical reliability of 3-D ICs containing through silicon vias," in 2009 59th Electronic Components and Technology Conference, pp. 630-634 (2009).
[26] K. Athikulwongse, A. Chakraborty, J.-S. Yang, D. Z. Pan, and S. K. Lim, "Stress-driven 3D-IC placement with TSV keep-out zone and regularity study," in 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 669-674 (2010).
[27] L. J. Ladani, "Numerical analysis of thermo-mechanical reliability of through silicon vias (TSVs) and solder interconnects in 3-dimensional integrated circuits," Microelectronic Engineering, vol. 87, no. 2, pp. 208-215 (2010).
[28] J.-S. Yang, K. Athikulwongse, Y.-J. Lee, S. K. Lim, and D. Z. Pan, "TSV stress aware timing analysis with applications to 3D-IC layout optimization," in Proceedings of the 47th Design Automation Conference, 2010, pp. 803-806(2010).
[29] M. Jung, X. Liu, S. K. Sitaraman, D. Z. Pan, and S. K. Lim, "Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC," in 2011 IEEE/Acm International Conference on Computer-Aided Design , pp. 563-570 (2011).
[30] Kwon, WS Alastair, DT Teo, KH Gao, S Ueda, T Ishigaki, T Kang, KT Yoo, WS ., "Stress evolution in surrounding silicon of Cu-filled through-silicon via undergoing thermal annealing by multiwavelength micro-Raman spectroscopy," Applied Physics Letters, vol. 98, no. 23, p. 232106 (2011).
[31] Z. Xu and J.-Q. Lu, "High-speed design and broadband modeling of through-strata-vias (TSVs) in 3D integration," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 1, no. 2, pp. 154-162 (2011).
[32] Heryanto, A Putra, Wahyuaji Narottama Trigg, A Gao, S Kwon, WS Che, FX Ang, XF Wei, J I Made, R Gan, Chee Lip, "Effect of copper TSV annealing on via protrusion for TSV wafer fabrication," Journal of Electronic Materials, vol. 41, pp. 2533-2542 (2012).
[33] J. Pang and J. Wang, "The thermal stress analysis in 3D IC integration with TSV interposer," in 2012 13th International Conference on Electronic Packaging Technology & High Density Packaging, pp. 725-730 (2012).
[34] S.K. Ryu, K.H. Lu, T. Jiang, J.H. Im, R. Huang, and P. S. Ho, "Effect of thermal stresses on carrier mobility and keep-out zone around through-silicon vias for 3-D integration," IEEE Transactions on Device and Materials Reliability, vol. 12, no. 2, pp. 255-262 (2012).
[35] M.Y. Tsai, P.S. Huang,C.Y. Huang, H. Jao,B. Huang, B. Wu, Y.Y. Lin, W. Liao, J. Huang, L. Huang, "Investigation on Cu TSV-induced KOZ in silicon chips: Simulations and experiments," IEEE Transactions on Electron Devices, vol. 60, no. 7, pp. 2331-2337 (2013).
[36] J. Zhang, L. Zhang, Y. Dong, H.Y. Li, C.M. Tan, G. Xia, C.S. Tan, "The dependency of TSV keep-out zone (KOZ) on Si crystal direction and liner material," in 2013 IEEE International 3D Systems Integration Conference (3DIC), pp. 1-5 (2013).
[37] Y. Zhu, J. Zhang, H. Y. Li, C. S. Tan, and G. Xia, "Study of near-surface stresses in silicon around through-silicon vias at elevated temperatures by Raman spectroscopy and simulations," IEEE Transactions on Device and Materials Reliability, vol. 15, no. 2, pp. 142-148 (2015).
[38] L. Spinella, M. Park, J.-h. Im, P. Ho, N. Tamura, and T. Jiang, "Effect of scaling copper through-silicon vias on stress and reliability for 3D interconnects," in 2016 IEEE International Interconnect Technology Conference/Advanced Metallization Conference (IITC/AMC), pp. 80-82 (2016).
[39] H.-Y. Tsai and C.-W. Kuo, "Thermal stress and failure location analysis for through silicon via in 3D integration," Journal of Mechanics, vol. 32, no. 1, pp. 47-53 (2016).
[40] Y. Pan, F. Li, H. He, J. Li, and W. Zhu, "Effects of dimension parameters and defect on TSV thermal behavior for 3D IC packaging," Microelectronics Reliability, vol. 70, pp. 97-102 (2017).
[41] F Huang, Z Fan, X Chen, Y Liu, S Zhang, Y Wang, Y Jiang, "Research on TSV thermal-mechanical reliability based on finite element analysis," in 2019 Prognostics and System Health Management Conference (PHM-Qingdao), pp. 1-8 (2019).
[42] G. Jalilvand, O. Ahmed, N. Dube, and T. Jiang, "The effect of pitch distance on the statistics and morphology of through-silicon via extrusion," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 11, no. 6, pp. 883-891, (2021).
[43] M. Moore, "International roadmap for devices and systems," Accessed: Jan, (2020).
[44] M. Motoyoshi, "Through-silicon via (TSV)," Proceedings of the IEEE, vol. 97, no. 1, pp. 43-48 (2009).
[45] S. W. Yoon, D. W. Yang, J. H. Koo, M. Padmanathan, and F. Carson, "3D TSV processes and its assembly/packaging technology," in 2009 IEEE International Conference on 3D System Integration, pp. 1-5 (2009).
[46] X. Zhang, T.C. Chai, J.H. Lau, C.S. Selvanayagam, K. Biswas, S. Liu, D. Pinjala, G.Y. Tang, Y.Y. Ong,S.R.Vempati, E. W., H.Y. Li, E.B. Liao, N. Ranganathan, V. Kripesh, J. Sun, John Doricko, C. J. Vath,"Development of through silicon via (TSV) interposer technology for large die (21× 21mm) fine-pitch Cu/low-k FCBGA package," in 2009 59th Electronic components and technology conference, pp. 305-312 (2009).
[47] L. Hofmann, R. Ecke, S. E. Schulz, and T. Gessner, "Investigations regarding Through Silicon Via filling for 3D integration by Periodic Pulse Reverse plating with and without additives," Microelectronic Engineering, vol. 88, no. 5, pp. 705-708 (2011).
[48] A. Pires Singulani, "Advanced methods for mechanical analysis and simulation of through silicon vias," Technische Universität Wien (2014).
[49] A. Redolfi, D. Velenis, S. Thangaraju, P. Nolmans, P. Jaenen, M. Kostermans, U. Baier,E. Van Besien, H. Dekkers, T. Witters, N. Jourdan, A. Van Ammel, K. Vandersmissen, S. Rodet, H.G.G. Philipsen, "Implementation of an industry compliant, 5× 50μm, via-middle TSV technology on 300mm wafers," in 2011 IEEE 61st Electronic Components and Technology Conference (ECTC), pp. 1384-1388 (2011).
[50] S Van Huylenbroeck, M Stucchi, Y Li, J Slabbekoorn, N Tutunjyan, S Sardo, N Jourdan, "Small pitch, high aspect ratio via-last TSV module," in 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), pp. 43-49 (2016).
[51] R. E. Hummel, Electronic Properties of Materials. Springer (2011).
[52] R. C. Jaeger, J. C. Suhling, and A. A. Anderson, "A [100] silicon stress test chip with optimized piezoresistive sensor rosettes," in 1994 Proceedings. 44th Electronic Components and Technology Conference, pp. 741-749 (1994).
[53] Yan, Jhih-Yang Jan, Sun-Rong Huang, Yi-Chung Lan, Huang-Siang Liu, CW Huang, Y-H Hung, Bigchoug Chan, K-T Huang, Michael Yang, M-T, "Compact modeling and simulation of TSV with experimental verification," in 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) , pp. 1-2 (2016).
[54] J. Wortman and R. Evans, "Young's modulus, shear modulus, and Poisson's ratio in silicon and germanium," Journal of Applied Physics, vol. 36, no. 1, pp. 153-156 (1965).
[55] F. P. Incropera, D. P. DeWitt, T. L. Bergman, and A. S. Lavine, Fundamentals of Heat and Mass Transfer. Wiley New York (1996).
[56] T. L. Bergman, T. L. Bergman, F. P. Incropera, D. P. Dewitt, and A. S. Lavine, Fundamentals of Heat and Mass Transfer. John Wiley & Sons (2011).
[57] H.-H. Lee, Finite element simulations with ANSYS Workbench 18. SDC publications (2018).
[58] H.-H. Lee, "Taguchi Methods: Principles and Practices of Quality Design; Gau Lih Book Co," Ltd.: New Taipei, Taiwan (2011).
[59] W.H. Li, " Reducing TSV dimensions by Taguchi Method ", thises,Department of Engineering Science National Cheng Kung University,pp.1-74 (2017).