於本論文的開頭，我們首先探討兩種製備二硫化鉬薄膜的方法，並發現由化學氣相沉積法所製備的二硫化鉬薄膜比起由濺鍍後硫化方式製備的薄膜在製作成電晶體後擁有著更好的元件表現。接下來，我們嘗試優化單層二硫化鉬電晶體的接觸金屬，將原本的銻替換為耐酸鹼腐蝕的金。實驗結果顯示，儘管金的功函數不匹配，其優秀的結晶性仍使其與半導體形成良好接觸，此外，我們還發現隨著提高接觸金屬的沉積溫度，接觸金屬的結晶性有逐漸增強的趨勢，且元件的接觸電阻也隨之降低使其性能獲得了提升。隨後將目光聚焦於多層二硫化鉬電晶體的應用上，我們透過直接成長方式與逐層轉印方式來製備多層二硫化鉬電晶體並相互比較兩者的特性，發現透過逐層轉印的方式，可以克服多層材料成長過程中上層材料成長可能導致下層材料受損的風險，從而獲得更好的元件特性。這種方法甚至能夠進一步構建參層二硫化鉬電晶體，不僅增加了載子通道數，還同時提升了電極與材料間的接觸品質，降低界面接觸電阻，使得元件性能顯著提升。藉由以上種種優化工作，本文在二硫化鉬底閘極場效電晶體的開態電流數值方面提升約238倍；場效電子遷移率則提升約172倍。觀察由逐層轉印製備的多層二硫化鉬電晶體元件，由於具備優良的接觸品質，因此多層薄膜內的電子濃度顯著提高，表示多層二維材料層內儲存的電荷數目大幅增加。藉此特點，我們進一步發展了二硫化鉬記憶體。通過蝕刻參層二硫化鉬薄膜的上層，形成孤立的二硫化鉬層作為電荷儲存層，並以下層二硫化鉬薄膜作為電荷傳輸層，構建了二硫化鉬記憶體。透過暫態曲線、讀寫循環曲線等量測方式，我們分析了元件的讀取維持時長、操作速度、操作電壓等，成功構築了一個只有寥寥幾個原子厚度的二維材料記憶體。

In this thesis, we investigate two growth methods for Molybdenum disulfide (MoS₂) thin films and find that films prepared by chemical vapor deposition (CVD) exhibit superior characteristics compared to those prepared by post-sulfurization of sputtered films. Subsequently, we optimize single-layer MoS₂ transistors by replacing Sb/Au electrodes with gold (Au) due to its high resistance to acid and alkali corrosion. Both types of electrodes show similar device characteristics, attributed to gold's excellent crystalline properties. Further optimization by increasing the deposition temperature of the contact metal enhances its crystallinity, reduces contact resistance, and improves performance. For multi-layer MoS₂ transistors fabricated through sequential transferring method, significantly enhanced device performances are observed due to the increased number of carrier channels and the improved contact quality between the electrodes and the material. The on-state current of the MoS₂ bottom-gate field-effect transistor increased by 238 times and field-effect mobility by 172 times. Due to the excellent contact quality, the electron concentration within the multi-layer thin films significantly increases. Utilizing this phenomenon, we have developed MoS₂ memories. Through ALEs to create isolated MoS2 charge storage layers on top of the MoS2 channel, memory operations are observed for the device. We have demonstrated long storage times and write-read-erase-read cycles of the MoS2 memory. 2D material memories with thicknesses down to few atomic layers are demonstrated, which is advantageous for the further line width shrinkage of memory devices.

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