電子系統層級硬體模擬中大量使用OSCI (Open SystemC Initiative) 所提供的SystemC函式庫作為主要模擬工具。SystemC所製作的硬體模擬系統經常使用於SoC(System-on-Chip)設計流程中做為虛擬開發平台。但也由於SoC設計的複雜度相當高，因此SystemC硬體模擬的執行效能就成為一個相當重要的問題。由於原始OSCI所提供的SystemC核心無法在SMP(Symmetric Multi-Processor)電腦架構下充分利用每個處理器的計算資源，因此這篇論文中我們針對原始OSCI版的SystemC核心提出的一個有效的平行化方式。這篇論文中主要說明平行化SystemC核心的實作項目及細節，另外為了減少執行緒切換時所需的額外計算消耗並增進平行的效能我們在此提出了多執行緒之多對一映射方式並詳加說明。

實驗部分我們使用了各種測試資料去展示對於平行核心的影響因素，實驗部分包含有計算量的測試和符合實際模擬需求的測試，其中在四顆處理器的機器上模擬硬體晶片內網路 (Network-on-Chip)，其執行時間為原始核心的三分之一。另外，由於修改造成的差異隱藏於函式庫內部，在使用平行化SystemC核心時完全不需要更改使用者撰寫的SystemC原始碼。

SystemC is a well-known open source library for electronic system level (ESL) modeling and simulation. The SystemC-based simulators are often served as virtual platforms in a SoC design flow. Since the complexity of SoC(System-on-Chip) designs are usually tremendous, the simulation efficiency of the sequential official OSCI(Open SystemC Initiative) SystemC simulation kernel become a critical issue. Also, it cannot be benefited from modern multi-core architectures. In this thesis, an effective parallel SystemC simulation kernel is proposed. The implementation issues and details of parallelizing the standard kernel are expatiated. SystemC processes are mapped to concurrent threads by many-to-one mapping. Also, the overhead of context switch is greatly reduced to achieve an effective parallelization.
Various benchmarks are used to show the significance of proposed kernel. Evaluation includes common computational tasks and a real-case system. The speed-up can be three times more when a model of Network-on-Chip Simulator simulated on a four-core computer. The modifications are transparent to SystemC applications, the source codes of applications require no modification when adopting to the proposed parallelized SystemC kernel.

[1] http://www.systemc.org/home/, Open SystemC Initiative, accessed August 2010
[2] IEEE Std 1666, ‘IEEE Standard SystemC Language Reference Manual’, 2005
[3] Chopard, B., Combes, P. and Zory, J.: ‘A Conservative Approach to SystemC Parallelization’, Proc. Workshop on Scientific Computing in Electronics Engineering, May 2006, pp. 653-660
[4] Huang, K., Bacivarov, I., Hugelshofer, F. and Thiele, L.: ‘Scalably Distributed SystemC Simulation for Embedded Applications’, Proc. Int. Symposium on Industrial Embedded Systems, June 2008, pp. 271-274
[5] Nanjundappa, M., Patel, H.D. and Jose, B.A., and Shukla, S. K.: ‘SCGPSim: A fast SystemC simulator on NVIDIA GPUs’, NVIDIA GPU Technology Conference, 2009
[6] Perez , D. G., Mouchard, G. and Temam, O.: ‘A New Optimized Implementation of the SystemC Engine using Acyclic Scheduling’, Proc. Conf. on Design, Automation and Test in Europe, Feb 2004, pp. 552-557
[7] Ezudheen, P. and Chandran, P., Chandra, J., Simon, B.P. and Ravi, D.: ‘Parallelizing SystemC Kernel for Fast Hardware Simulation on SMP Machines’, Workshop on Principles of Advanced and Distributed Simulation , June 2009
[8] Quinn Michael J: ‘Parallel Programming in C with MPI and OpenMP’(McGra-Hill Inc., 2004)
[9] http://www.gnu.org/software/libc/, GNU POSIX Thread Library, accessed August 2010
[10] http://screamlabopensource.blogspot.com/, SCREAM Lab, OpenESL, accessed August 2010
[11] Shih, T.Y., Liao, W.S., Fu, W.Y., Dai, S.F. and Su, Alvin W.Y.: ‘An Integrated Electronic System Level Design and Simulation Environment’, The 20th VLSI Design/CAD Symposium, Taiwan, Aug. 2009
[12] Shih, T.Y., Wang, Y.L., Liou, J.R., Su, Alvin W.Y., Chen, C.H., Lee K.L.: ‘OpenESL and Its Co-Simulation Framework for Heterogeneous Tools’, Internal Symposium on VLSI Design, Automation and Test, HsinChu, Taiwan, April 2010
[13] http://www.systemc.org/downloads/standards/, SystemC 2.2, accessed August 2010
[14] Conway, M.E. Design o f a separable transition-diagram compiler. Comm. A C M 6, 7 (July 1963), 396-408.
[15] http://ark.intel.com/Product.aspx?id=35365, accessed August 2010
[16] OpenCores, http://opencores.org/
[17] http://www.arm.com/, ARM,accessed August 2010
[18] http://www.systemc-ams.org/, SystemC AMS