為提高每晶粒之流明通量，高功率垂直結構氮化鎵基發光二極體之發展以大面積及高發光效率為主流。隨著元件面積的上升，輸入電流無法均勻分佈整體元件，使得寄生串聯電阻變大及順向壓降(Forward voltage drop, VF)上升。為改善此一現像，透明導電層(transparent conduction layer, TCL)的使用、表面結構的設計(surface engineering)與電極圖案之設計常被採用以為因應。
習知電極設計之圖形，多是由等線寬金屬線條所組成之幾何圖形。雖為增加電流擴散均勻度並降低光遮避耗損，電極之間距安排多依循n-GaN上之擴散長度以為設計準則。然於電極金屬導線進行電流傳輸之時，會形成壓降，深深影響主動層上擴散電流之分佈，使得整體電流分佈之均勻性下降，影響有效導通面積與光析出效率。
本論文旨在提出一新穎漸變式電極之設計，透過金屬電極間距之恰當安排，降低光由電極下方析出所遭遇之遮蔽耗損。所採用線寬漸變之設計，使得在電極遮蔽率相同的條件之下，能有效改善電流於導線上傳輸之壓降不均，使得元件在同一操作電壓時，整體電流分佈均勻度上升，增益其光輸出之能力，並降低其串聯阻值，提升光電轉換效率。經實驗證明，在元件大小同為1000×1000 m2，線間距同為125 m時，所提出之電極設計(線寬由25 m漸變至15 m)，於4 V時，串聯阻值由2.38 Ω降至1.88 Ω，有最佳光電轉換效率，與傳統等線寬元件相較，改善幅度達7 %。

Vertical structure GaN-based light-emitting diodes (VM-LEDs) are commonly made in large areas with high intensity to increase the luminous flux in each crystal. As the area increases, the current distribution over the compound becomes uneven, thus increased stray resistance and forward voltage drop (VF). Use of transparent conducting layer (TCL), surface engineering, and exclusively shaped electrode are the typical solution to this phenomenon.
Most prior arts in electrode design are constructed via equal width metallic traces which the current spreading length of n-GaN is adapted as the spacing reference. Said layout may have increased the evenness of current and decreased the masking loss of light, but it also caused a voltage drop as current traveled across metal traces. Such voltage drop caused unevenness of the current distribution on the active region; effective conducting area and light emitting efficiency is also affected.
The primary purpose of the present thesis is to provide a gradational electrode design. Masking loss of light is decreased by proper spacing of electrodes. The gradual change in trace width decreased the voltage drop, thus enabling better current distribution under same masking rate and operating voltage. As a result, stray resistance is decreased, light emitting capability and photoelectric transfer efficiency is increased.
During the experiment, components are sized to 1000×1000 m2 with 125 m trace spacing and operated at 4 volt. The proposed electrode design (25 m to 15 m gradation) is capable of decrease the total resistance from 2.38Ω to 1.88Ω. There is a 7 % increase in efficiency when compared to components with traditional equal-width design.

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