| 研究生: |
黃義方 Huang, Yi-Fang |
|---|---|
| 論文名稱: |
基於風險控管的低延遲權證交易系統及其快速FAST協定解碼器的NetFPGA設計與實作 Low-Latency Warrants Trading System of Risk Management with Speedy FAST Protocol Decoder on NetFPGA |
| 指導教授: |
張燕光
Chang, Yeim-Kuan |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 資訊工程學系 Department of Computer Science and Information Engineering |
| 論文出版年: | 2019 |
| 畢業學年度: | 107 |
| 語文別: | 英文 |
| 論文頁數: | 138 |
| 中文關鍵詞: | 金融訊息交換協定 、適用於傳輸之金融訊息交換協定壓縮方法 、高頻交易造市交易 、NetFGPA SUME 、權證風險控管 、TCP/UDP協定解碼器 |
| 外文關鍵詞: | Financial Information eXchange Protocol (FIX), FIX Adapted for Streaming (FAST), High frequency trading (HFT), Market-making trading, NetFPGA SUME, Warrant Risk control, TCP/UDP protocol decoder |
| 相關次數: | 點閱:185 下載:10 |
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在股票交易中,低延遲的傳送可以幫助投資人在市場的交易順序上取得優先的位置。傳統上,市場的交易數據會使用軟體來解碼,然而,作業系統的排程和調度會導致高延遲的解碼速度,於是出現高頻交易 (High Frequency Trading)的技術。高頻交易主要利用硬體低延遲的特性,如:GPU、ASIC或FPGA來解碼訊息,使之對市場數據的處理延遲能維持在微秒等級。搭配自動化的交易系統,節省交易訊息傳輸、策略判斷的時間延遲來達到賺取股票買賣的價差的目的。造市行為是目前最被廣泛使用的高頻交易策略之ㄧ。對造市者來說,風險控管是最重要的一環,為了防止造市的過程使自身產生虧損,券商必須根據即時市場行情,隨時準備刪除已經送出的委託買/賣訂單。我們運用高頻交易的特性在權證交易的風險管控上,設計一個低延遲且全自動的刪單處理系統。我們設計的系統針對台灣證券交易所規範的FAST(FIX Adapted for Streaming)協定及金融訊息交換協定(FIX4.4版本)為解碼目的,並使用NetFPGA SUME作為實作系統之平台;系統本身除了傳輸層TCP協定的基礎連線維持外,針對FIX協定連線傳輸資料的功能也實作於系統中;我們也在FPGA上實作Cuckoo hashing演算法,利用FPGA上的on-chip Memory,實現儲存多筆相同標的物,不同價格的訂單資訊紀錄及快速搜尋股票代號對應之委託簿內容的功能;我們依據股票五檔訂單數量的即時變動資訊來預測未來股價的漲跌,藉此決定要刪除市場上不同價位的買單和賣單。此系統針對台灣證交所的集中市場一般行情資訊封包做解碼,一個封包可以在平均31.25(37.5) ns內完成;從收到完整市場行情封包到產生對應的第一筆刪單請求封包也只需要平均469 ns。我們的系統可提供造市者關於FAST協定的低延遲解碼器,並透過FPGA的特性可以快速更改交易策略,使風險控管系統更具實用性與便利性。
In stock trading, low-latency transfers can help investors prioritize the order of transactions in the market. Traditionally, market transaction data is decoded using software. However, the task scheduling executed in the operating system leads to high latency, so high-frequency trading (High Frequency Trading) technology appears. High-frequency trading mainly uses the low-latency features in hardware such as GPU, ASIC or FPGA to decode messages so that the processing delay for market data can be maintained at the microsecond level. In the automated trading system, the time delay of trading message transmission and strategy judgment need to be reduced to achieve the purpose of earning the spread of stock trading. The market-making behavior is currently the most widely used high-frequency trading strategy. The market-making refers to the continuous limit order on both sides of the order book to provide liquidity and earn the spread. For market makers, risk control is the most important part. To prevent the market making process from causing losses, brokers must be ready to delete the buy/sell orders that have been sent according to the immediate market conditions. We use the characteristics of high-frequency trading to design a low-latency and fully automatic deletion processing system for the risk management of warrant trading. We design and improve the decoding process for the FAST (FIX Adapted for Streaming) Protocol and the Financial Information Exchange Protocol (FIX4.4 version) regulated by the Taiwan stock exchange and using NetFPGA SUME as the implementation platform. The system maintains the basic connection of the TCP protocol, and the function of transmitting data for the FIX protocol is also implemented. The Cuckoo hashing algorithm is implemented on the FPGA platform which realizes the function of storing multiple order information with different prices, and quick search for the contents of the order book corresponding to the stock code. We use the real-time information on the number of orders to predict the rise and fall of future stock prices, to decide when to delete the buy or sell orders in the market. Our proposed system decodes the FAST market information packet of the Taiwan Stock Exchange. A packet can be completely decoded within an average latency of 31.25(37.5) ns. It takes only an average of 469 ns from receiving complete market packet to generating the corresponding FIX order cancel request packets. Our system provides market makers with low-latency decoder for the FAST protocol implemented on FPGA can quickly change the trading strategy and make the risk control system more practical and convenient.
[1]M.J. Barclay, T. Hendershott, and D.T. McCormick. “Competition among trading venues: Information and trading on electronic communications networks.” The Journal of Finance 58, 2637-2665, 2003.
[2]U.S. Securities and Exchange Commission. “Equity Market Structure Literature Review Part II: High Frequency Trading”,March 18,2014https://www.sec.gov/marketstructure/research/hft_lit_review_march_2014.pdf
[3]Y Simaan, “Market maker quotation behavior and pretrade transparency”, Journal of Finance 58, 1247-1267, 2003
[4]M. Chlistalla, “High-frequency trading Better than its reputation?” Deutsche Bank research report, 2011.
[5]行政院金融監督管理委員會證券期貨局。 “淺談高頻交易之發展與近況” 。https://www.twse.com.tw/ch/products/publication/download/0001000928.pdf
[6]Y Simaan, “Market maker quotation behavior and pretrade transparency”, Journal of Finance 58, 1247-1267, 2003
[7] Y Amihud, “Dealership market: Market-making with inventory”, Journal of Financial Economics 8, 311-353, 1980
[8]R Pottathuparambil, “Low-latency FPGA Based Financial Data Feed Handler”, 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 93-96
[9]Han Li,Fu Y.,Liu T. and Wang J., “Fast Protocol Decoding in Parallel with FPGA Hardware”, 2014 IEEE 17th International Conference on Computational Science and Engineering,1-5
[10]Tang Q., Su M., Jiang L., Yang J., and Bai X., “A Scalable Architecture for Low-Latency Market-Data Processing on FPGA ,2016 IEEE Symposium on Computer and Communication (ISCC),1-7
[11]M. Sadoghi, M. Labrecque, H. Singh, W. Shum, and H. Jacobsen, “Efficient Event Processing through Reconfigurable Hardware for Algorithmic Trading”, Proceedings of the VLDB Endowment, Vol. 3, Issue 1-2, pages 1525-1528, September 2010
[12]He C., Fu H., W. Luk, Li W., and Yang G., “Exploring the Potential of Reconfigurable Platforms for Order Book Update”, 2017 IEEE 27th International Conference on Field Programmable Logic and Applications (FPL),1-8
[13]G. W. Morris, D. B. Thomas and W. Luk, "FPGA Accelerated Low-Latency Market Data Feed Processing" 2009 17th IEEE Symposium on High Performance Interconnects, pages 83-89.
[14]M. Dvořák and J. Kořenek, “Low latency book handling in FPGA for high frequency trading.” 2014 17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, pp 175-178.
[15]Zhou L., Jiang J., Liao R., Yang T.,and Wang C. , “FPGA Based Low-Latency Market Data Feed Handler”,2014 NCCET ,Communications in Computer and Information Science, vol 491,pages 69-77.
[16]V. Agarwal, D. A. Bader, Lin D., Liu L., and D. Pasetto, “Faster FAST:multicore acceleration of streaming financial data”,2009 Journal of Computer Science-Research and Development ,vol. 23 ,pages 249-257 .
[17]Dou Y.,Zhou Y.,and Xin B., “An Accelerator for Decoding Market Data Based on FPGA”, 2019 Journal of Circuits, Systems and Computers,Vol.28 ,No.3,pages 1-16.
[18]台灣證券交易所電腦規劃部。NEW FIX 4.4電文規範。http://www.twse.com.tw/zh/brokerService/brokerServiceComputer
[19]NetFPGA Organization, “NetFPGA SUME Public”. https://github.com/NetFPGA/NetFPGA-SUME-public/wiki
[20]台灣證券交易所電腦規劃部。FIX/FAST資訊傳輸系統連線作業手冊。https://www.twse.com.tw/docs1/data01/market/public_html/1010917-1010602204-1.pdf
[21] Y.-K. Chang and W.-L. Wang, “A Low-Latency Warrants Trading Scheme of Risk Management Using NetFPGA SUME”
[22]台灣證券交易所電腦規劃部。台灣證券證交所資訊傳輸作業手冊。版 本 B.11.17。http://www.twse.com.tw/zh/brokerService/brokerServiceComputer
[23]NetFPGA Organization, “NetFPGA SUME Reference Router”. https://github.com/NetFPGA/NetFPGA-SUME-public/wiki/NetFPGA-SUME-Reference-Router
[24]Xilinx, “AXI4-LITE IP Interface document”. https://www.xilinx.com/products/intellectual-property/axi_lite_ipif.html#documentation
[25] Y.-K. Chang and C.Y. Li, “Prototype Implementation of a low-latency Automated Stock Trading System on NetFPGA”
[26]C Leber, “High Frequency Trading Acceleration using FPGAs”, 2011 21st International Conference on Field Programmable Logic and Applications, 317-322
[27]Mellanox technologies Solution Brief, 2015, http://www.mellanox.com/related-docs/applications/SB_HighFreq_Trading.pdf
[28]FAST protocol specification
http://ftp.moex.com/pub/FAST/Spectra/test/spectra_fastgate_en.pdf
[29] A. Boutros, B. Grady , M. Abbas and P. Chow , “Build Fast, Trade Fast: FPGA-based High-Frequency Trading using High-Level Synthesis”, 2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1-6
[30]Xilinx, “Vivado High-Level Synthesis”. https://www.xilinx.com/products/design-tools/vivado/integration/esl-design.html
[31]D. Pasetto,K. Lynch,and R. Tucker, “Ultra low latency market data feed on IBM PowerENTM”,Journal of Computer Science –Research and Development , Vol. 26,pages 307-315, 2011.
[32]R Pagh, “Cuckoo Hashing”, Journal of Algorithms 51, 122-144, 2004
[33]B. Jenkins, “A Survey of Hash Functions” http://burtleburtle.net/bob/hash/doobs.html
[34]QuickFIX Open Source http://www.quickfixengine.org/
[35]Xilinx, “AXI Interconnect”. https://www.xilinx.com/products/intellectual-property/axi_interconnect.html
[36]N. Zilberman, NetFPGA SUME Tutorial Slide, Unervisity of Cambridge. http://www.cl.cam.ac.uk/research/srg/netos/projects/netfpga/workshop/fpl-august-2015/material/slides/2015_FPL_tutorial.pdf
[37]J.Touch and B. Parham , “Implementing the Internet Checksum in Hardware”,Network Working Group ,Request for comments :1936.https://tools.ietf.org/pdf/rfc1936.pdf
[38]台灣證券交易所電腦規劃部。FIX/FAST測試資料_20150901和FIX/FAST行情傳輸系統Template。https://www.twse.com.tw/zh/brokerService/brokerServiceComputer
[39]mFAST open source http://objectcomputing.github.io/mFAST/
[40]J. W. Lockwood, A. Gupte, N. Mehta, M. Blott, T. English and K. Vissers, “A Low-Latency Library in FPGA Hardware for High-Frequency Trading (HFT).” 2012 IEEE 20th Annual Symposium on High-Performance Interconnects, pages 9-16, Santa Clara, CA, 2012.
[41]X.Shen,J. Jiang,L. Zhou,T. Yang and L.Chen, “A market data feeds processing accelerator based on FPGA”,Journal of Computer Engineering and Technology : NCCET 2013, Communications in Computer and Information Science,Vol.396,pages 44-52