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研究生: 張博凱
Chang, Po-kai
論文名稱: 高效率影像脈衝雜訊移除晶片設計
An Efficient Chip for Image Impulse Noise Removal
指導教授: 陳培殷
Chen, Pei-yin
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Department of Computer Science and Information Engineering
論文出版年: 2008
畢業學年度: 96
語文別: 中文
論文頁數: 63
中文關鍵詞: 去雜訊硬體實作
外文關鍵詞: denoise, hardware implementation
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  • 在許多數位影像應用如:掃描與影印技術、醫學影像或是人臉辨識等,往往因為影像的獲得或傳送過程受到雜訊的污染,而造成了影像視覺品質的降低,故去除雜訊的技術是影像處理上非常重要的一個議題。因為去除雜訊的技術常被包含在許多需要滿足即時處理的電子產品應用中,所以,一個效果良好、低複雜且適合以VLSI硬體實作的影像去雜訊技術是不可避免的。
    在本論文中,我們提出兩個可保留邊緣特性的去雜訊技術,來分別移除fixed-valued脈衝雜訊與random-valued脈衝雜訊。針對要處理影像中的每一個像素,先以一個3×3的工作視窗來偵測此像素是否為雜訊點並找尋此工作視窗中存在的方向邊緣,用以預估此像素的重建值。若此像素被偵測為雜訊點,則以此重建值取代它。
    實驗結果證明,本論文提出的方法不管在數學測量或肉眼針對所設計的方法,我們也發展出一個高速的VLSI架構並用Verilog 硬體描述語言實現。根據SYNOPSYS的Design Vision和TSMC’s 0.18μm的標準元件庫合成結果,此二電路所需的邏輯閘數目分別為12K與18K,工作於5 ns的時脈達到200百萬像素/秒的處理量,換句話說,我們有足夠的速度即時處理WQSXGA (3200×2048)每秒30張影像的格式。

    In many applications, such as medical imaging, scanning techniques and face recognition, images are often corrupted by noise during image acquisition and transmission. Thus, the denoising technique becomes a very important issue in image preprocessing. In many practical real-time applications, the denoising process is included in end-user equipment, so a good lower-complexity denoising technique, which is simple and suitable for low-cost VLSI implementation, is needed.
    In this paper, two efficient edge-preserving denoising techniques are proposed to remove the fixed-valued impulse noise and random-valued impulse noise, respectively. They can preserve the edge features efficiently by finding a directional edge existed in the window centered on the current pixel and using the edge to determine the reconstructed value of current pixel. Extensive experimental results demonstrate that our method can obtain better performances in terms of both subjective and objective evaluations than those state-of-the-art impulse denoising techniques.
    The VLSI architectures of the proposed designs were implemented by using Verilog HDL. We used SYNOPSYS Design Vision to synthesize the designs with TSMC’s 0.18μm cell library. Synthesis results show that the two denoising circuits contain 12K and 18K gate counts, respectively. Both of them work with a clock period of 5 ns and can achieve a processing rate of 200 mega pixels per second which is quick enough to process a video resolution of WQSXGA (3200×2048) at 30 fps in real time.

    圖目錄 VIII 第一章 緒論 10 1.1 研究背景 10 1.2 研究動機 10 1.3 論文組織 11 第二章 相關文獻探討 12 2.1 脈衝雜訊(Impulse Noise) 12 2.2 現存的去雜訊演算法 12 2.2.1 New Impulse Detector for Switching Median Filter (NID) 12 2.2.2 Differential Rank Impulse Detector (DRID) 13 2.2.3 Simple Fuzzy Impulse Detector (SFID) 14 2.2.4 Alpha-trimmed mean-based method (ATMBM) 15 2.2.5 Decision-Based Algorithm (DBA) 15 2.2.6 Directional Weight Median (DWM) 16 第三章 所提出的雜訊移除演算法 18 3.1 Fixed-valued 脈衝雜訊移除演算法 18 3.2 Random-valued 脈衝雜訊移除演算法 25 第四章 去雜訊演算法之硬體實現 29 4.1 Fixed-valued 脈衝雜訊移除演算法硬體架構 29 4.2 Random-valued 脈衝雜訊移除演算法硬體實作 35 4.3 管線化設計 39 第五章 模擬結果 43 5.1 Fixed-valued 脈衝雜訊移除演算法 43 5.2 Random-valued脈衝雜訊移除演算法 57 5.3 硬體模擬結果 61 第六章 結論與未來工作 62 6.1 結論 62 6.2 未來工作 62 參考文獻 63

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