| 研究生: |
杜少宏 Tu, Shao-Hung |
|---|---|
| 論文名稱: |
應用於水下影像強化之輕量化卷積神經網路電路設計 A Lightweight CNN-based Circuit for Underwater Image Enhancement |
| 指導教授: |
陳培殷
Chen, Pei-Yin |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 資訊工程學系 Department of Computer Science and Information Engineering |
| 論文出版年: | 2025 |
| 畢業學年度: | 113 |
| 語文別: | 中文 |
| 論文頁數: | 66 |
| 中文關鍵詞: | 水下影像 、VLSI 、影像增強 、卷積神經網路 |
| 外文關鍵詞: | Underwater image, VLSI, image enhancement, convolutional neural network |
| 相關次數: | 點閱:21 下載:0 |
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水下影像因光的吸收與散射作用導致色偏與對比度降低等問題,造成影像退化、品質不佳。近年來,有許多關於水下影像增強的研究文獻,大致可以分為基於深度學習的方法與非深度學習的方法。深度學習方法能有效提升影像品質,然而多數深度學習的方法架構複雜、參數量龐大,導致硬體實現困難,而非深度學習的方法則是在多變的水下環境往往無法取得穩定的影像增強品質。
本論文提出結合傳統影像增強演算法與輕量化卷積神經網路之水下影像增強模型架構。透過色彩校正、對比度增強等規則式演算法模組輔助網路特徵學習,有效降低模型參數量。此外,本論文亦將此網路架構於硬體實現。
實驗結果顯示,提出的方法在多變的水下影像場景中展現出穩定的增強效果,能避免嚴重失真的情況發生。儘管整體架構所需的參數量遠低於主流深度學習方法,所產出的影像品質在主觀視覺效果與客觀指標的評估仍不遜色於近期相關研究成果。
本論文提出的硬體架構使用Verilog HDL實現,Cell Library製程為TSMC 40nm,使用新思科技的Design Compiler合成。工作頻率可達200MHz ,電路面積為 208779 (〖μm〗^2),總功率消耗為 64.1545mW。實驗結果證明,此硬體設計具低成本之優勢,並適合部署於資源受限的平台。
Underwater images often suffer from quality degradation such as color distortion and reduced contrast due to light absorption and scattering effects. In recent years, numerous studies have been proposed for underwater image enhancement, which can be broadly categorized into deep learning-based and non-deep learning-based approaches. While deep learning methods can effectively improve image quality, they are often characterized by complex architectures and large parameter sizes, making hardware implementation challenging. On the other hand, non-deep learning methods typically fail to maintain stable enhancement performance under diverse underwater conditions. We propose a hybrid underwater image enhancement framework that combines traditional enhancement techniques with a lightweight convolutional neural network. The framework leverages modules such as color correction and contrast enhancement to assist in feature learning. Experimental results demonstrate that the proposed method achieves stable enhancement across various underwater scenes and avoids severe distortions. Despite having significantly fewer parameters compared to mainstream deep learning models, the proposed approach achieves competitive performance in both subjective visual quality and objective evaluation metrics. Moreover, the method is hardware-friendly and suitable for deployment on resource-constrained platforms.
The proposed hardware architecture is implemented using Verilog HDL and synthesized with TSMC 40nm cell library via Synopsys Design Compiler. For input images of size 256×256, the design operates at a clock frequency of 200 MHz, with a total circuit area of 208,779 μm² and a power consumption of 64.1545 mW.
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校內:2030-07-16公開