本篇論文主要的目的是研究12V/15V的p通道的高壓元件熱載子退化機制。在元件經過熱載子效應的stress後，針對元件重要的參數退化進行內部機制的研究分析，並且使用charge pumping的方法探討經熱載子stress後元件內部的接面陷阱(interface traps)或是電荷捕陷(charge traps)的產生機制。
研究中所使用的元件是p通道的高壓元件LDMOS，大致上可把該元件分成以下三個區域來探討內部的退化機制；通道區、閘極控制的漂移區、飄移區。元件經過熱載子的stress後，三個區域將會有不同的機制產生，並且導致到元件的參數偏移。
考量到實際電路應用時，即使p通道元件閘極也可能操作在正偏壓狀況，在結束元件的stress後，對元件閘極施予一個正偏壓探討元件修復(recovery)的機制，量測結果顯示，正偏壓對元件的參數將有修復的效果，但在charge pumping結果指出，對閘極控制的漂移區卻進一步有接面陷阱上升的趨勢，這樣現象也在本論文中有詳細的探討在該區可能發生的機制。

The major purpose in this thesis studies hot carrier stress induced degradations and mechanisms of 12V/15V p-channel High Voltage Device. As the device subjects hot carrier stress, the important parameter degradations of device are directed to analyze the mechanisms in device. Charge pumping method is used to study the generation mechanisms of interface trap and oxide trap in device after hot carrier stress.
The high-voltage device used in the thesis is p-channel Lateral Double Diffused MOSFETs (p-LDMOS). Generally speaking, it can be divided into three regions to discuss the device degradation mechanisms; channel region, gate controlled drift region and drift region. The device post stress will cause different degradation mechanisms in different region respectively and then results in device parameters shift.
The actual circuit applications are taken into account, even if p-channel transistor will be applied positive voltage to gate. As stress experiment is finished, a positive voltage applied to gate in order to study the recovery mechanisms of device. The result of measurement shows positive voltage will recover the parameter degradation. Nevertheless interface traps increased further in gate controlled drift region is observed by charge pumping measurement. The phenomenon will be discussed in detail what mechanisms occurred in each region.

[1] A. Moscatelli, A. Merlini, G. Croce, P. Galbiati, and C. Contiero, “LDMOS implementation in a 0.35μm BCD technology, ”ISPSD, pp.323, 2000.
[2] T. Terashima, et al., “Multi-voltage device integration technique for 0.5μm BiCMOS and DMOS process,” in Proc. ISPSD pp. 331-334 (2000).
[3] J. A. Van der Pol, et al., “A-BCD: An economic 100 V RESURF silicon-on-insulator BCD technology for consumer and automotive applications,” ISPSD, pp. 327-330 (2000).
[4] P. Moens, et al., “I3T80: A 0.35 μm based system-on-chip technology for 42 V battery automotive applications,” ISPSD, pp. 225-228 (2002).
[5] L.S Wong et al., “A very low power CMOS Mixed-Signal IC for Implantable Pacemaker Application”, Proceeding of the International Solid State Circuit Conference (ISSCC), pp. 318-319 (2004).
[6] Chenming Hu et al., “Hot-electron-Induced MOSFET Degradation-Model, Monitor, and Improvement”, IEEE JOURNAL OF SOLLID STATE CIRCUITS, VOL. SC-20, NO. 1, FEBRUARY (1985).
[7] Ong, T.C., Ko, P.K., Hu, C., ”Hot-carrier current modeling and device degradation insurface-channel p-MOSFETs” IEEE TRANSCATIONS ON ELECTRON DEVICES. VOL. 37. NO. 7. JULY (1990).
[8] Paul Heremans et al., “Analysis of the charge pumping Techniqure and Its Application for Evaluation of MOSFET Degradation”, IEEE TRANSCATIONS ON ELECTRON DEVICES. VOL. 36. NO. 7. JULY (1989)
[9] Stanley Wolf, “Silicon Processing for the VLSI Era,” Volume 3: The Submicron MOSFET (1995).
[10] Dieter K. Schroder, “Semiconductor Material and Device Characterization,” second edition
[11] Masakatsu Tsuchiaki, Hisashi Hara, Toyota Morimoto, and Hiroshi Iwai, “A New Charge Pumping Method for Determining the Spatial Distribution of Hot-Carrier-Induced Fixed Charge in p-MOSFET’s” IEEE TRANSCATIONS ON ELECTRON DEVICES. VOL. 40. NO. 10. OCTOBER (1993).
[12] BRIAN DOYLE, MARC BOURCRIE, JEAN-CLAUDE MARCHETAUX and ALAIN BOUDOU. “Interface state creation and charge trapping in the medium-to-high fate voltage range (Vd/2>2Vg>Vd) during hot-carrier stressing of n-MOS transistors” IEEE TRANSCATIONS ON ELECTRON DEVICES. VOL. 37. NO. 3. OCTOBER (1990).
[13] C. C. Cheng, K. C. Tu, and Tahui Wang, “Investigation of Hot Carrier Degradation Modes in LDMOS by Using A Novel Three-region Charge Pumping Technique,” IEEE IRPS, (2006).
[14] C. C. Cheng, J. F. Lin, T. Wang, T. H. Hsieh, J. T. Tzeng, Y. C. Jong, R. S. Liou, S. C. Pan, and S. L. Hsu, “Physics and characterization of various hot-carrier degradation modes in LDMOS by using a novel three-region charge pumping technique,” IEEE TDMR, vol. 6, NO. 3, (2006).
[15] S. K. Lee, C. J. Kim, J. H. Kim, Y. C. Choi, H. S. Kang and C. S. Song, “Optimization of Safe-Operating-Area Using Two Peaks of Body-Current in Submicron LDMOS Transistors”, Proceedings of 2001 International on Power Semiconductor Devices & ICs, Osaks
[16] J. F. Chen, K.-M. Wu, K.-W. Lin, Y.-K. Su, and S. L. Hsu, “Hot-carrier reliability in submicrometer 40V LDMOS transistors with thick gate oxide,” IRPS, pp. 560-564, (2005).
[17] FUMITOMO MATSUOKA, HIROSHI IWAI, HIROYUKI HAYASHIDA, KAORU HAMA, TOSHIAKI TOYOSHIMA, AND KENJI MAEGUCHI“Analysis of Hot-Carrier-Induced Degradation Mode on pMOSFET’s”, IEEE TRANSCATIONS ON ELECTRON DEVICES. VOL. 37. NO. 6. JUNE (1990)
[18] C. C. Cheng, J. W. Wu, C. C. Lee, J. H. Shao and T. Wang, “Hot Carrier Degradation in LDMOS Power Transistors”, IEEE Proceedings of 11st IPFA 2004, Taiwan
[19] P. Mones, F. Bauwens, M. Nelson and M. Tack, “ELECTRON TRAPPING AND INTERFACE TRAP GENERATION IN DRAIN EXTENDED PMOS TRANSISTORS”, IEEE 43RD Annual Intermational Reliability Physics Symposium, Sam Jose. (2005).
[20] P. Moens, G. Van den bosch, and G. Groeseneken, “Competing hot carrier degradation mechanisms in lateral N-type DMOS transistors,” IRPS, p.214 (2003).
[21] I. S. Al-kofahi, J. F. Zhang and G. Groeseneken, “On the hot hole induced post-stress interface trap generation in MOSFET’s”, IEEE (1996).
[22] Rudi Bellens, Erik de Schrijver, Greet Van den bosch, Guido Groeseneken, Paul Heremans, and Herman E. Maes, “On the Hot-Carrier-Induced Post-Stress Interface Trap Generation in n-channel MOS Transistors” IEEE (1994).
[23] I. S. Al-kofahi, J. F. Zhang and G. Groeseneken, “Continuing degradation of the SiO2/Si interface after hot hole stress”, J. Appl. Phys. 81 (6), 15 March (1997).