隨著半導體工業的發展，電晶體尺寸已逐漸微縮並面臨其物理極限，因此為了延續摩爾定律，高遷移率通道材料-鍺，因而被廣泛的研究。然而在眾多的研究當中，鍺材料的介面品質依然是高性能電晶體的一大瓶頸。
本論文研究以原子層沉積技術，沉積高介電常數之介電層，用來製備低等效氧化層厚度金氧半電容器。為了解決二氧化鍺在熱處理後容易裂解的現象，我們利用氨電漿處理對其進行表面改質，處理過後的氮氧化鍺相較於原材料有更好的熱穩定性並能提高介電層品質，且有助於穩定鍺表面狀態。當等效氧化層厚度微縮至次奈米技術節點時，閘極堆疊沉積前的晶圓表面狀態將變得越來越重要，不僅會影響到金屬沉積後退火對缺陷修補的有效性，也會反映在元件的性能上。再者，透過最佳化其製程參數，作者開發出等效氧化層厚度約為6 Å，磁滯為85 mV之低介面陷阱金氧半電容器。
最後我們利用一側壁選擇性蝕刻方法，成功地將最佳金氧半電容器條件應用於鍺基板全閘極環繞式場效電晶體上。實現次臨界擺幅為66mV/dec於n型全閘極環繞式場效電晶體；於p型上達成次臨界擺幅為67mV/dec。兩者皆有非常低的汲極引發位能障下降且電流開關比皆達到6個數量級。接著利用金屬連線，完成了反向器電路，並成功量測VTC轉換曲線，其電壓增益約為37 V/V，也驗證了此鍺基板全閘極環繞式場效電晶體，可實際應用於電路中的可行性。

For the development of semiconductor industry, the transistors dimension has gradually scaled down and faced its physical limitation. Thus, to extending the Moore’s Law, high mobility channel material, Ge, has been widely studied. Nevertheless, the interface quality of Ge is a bottleneck for high performance application.
In this thesis, we investigate the high-κ dielectric and interface layer fabricated on Ge MOS capacitor by atomic layer deposition (ALD). In order to solve the issue of GeO2 easily desorption after the thermal process, we implant in-situ NH3 plasma for interfacial layer modification. Compared to GeO2, GeON has higher thermal stability, which can enhance the dielectric quality and stable the Ge surface. When the EOT scaled down to the sub-nano region, the wafer surface condition prior to the gate stack deposition becomes more and more critical, which will influence the effectiveness of the PMA process for defect repair, and reflect in device performance. With the optimization of all the process parameters, we developed a HfO2/Al2O3/GeON/Ge gate stack with ultra-thin EOT of 6 Å, hysteresis of ~85 mV and low Dit.
Finally, we successfully fabricate high-κ gate stacks on Ge gate-all-around field-effect transistor (GAAFET), by using the sidewall selective etching method. The superior SS characteristics of 66 mV/dec. and 67 mV/dec with extremely low DIBL and high Ion/Ioff ratio about 6 order of magnitude were achieved for Ge n- and p-GAAFETs, respectively. With the metallization process, we completed the CMOS inverter circuit, and the voltage transfer characteristic (VTC) with the maximum voltage gain of 37 V/V was achieved. This verifies the feasibility of the Ge gate-all-around field-effect transistors that can practically apply in circuits.

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