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研究生： 黃智偉
Huang, Chih-Wei
論文名稱： 以氧化石墨烯層提升氧化鎵電阻式記憶體之電性研究
Switching Performance Enhancement in Gallium Oxide-based Multilevel RRAM Devices using Graphene Oxide Insertion Layer
指導教授： 王永和
Wang, Yeong-Her
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年： 2022
畢業學年度： 110
語文別： 英文
論文頁數： 100
中文關鍵詞： 電阻式記憶體 、氧化鎵 、石墨氧化物 、雙層結構 、多阻態儲存
外文關鍵詞： RRAM, Gallium oxide, Graphene oxide, Bilayer structure, Multilevel storage
相關次數： 點閱：391  下載：0 
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    • 近年來，電阻式隨機存取記憶體 (RRAM) 被認可為極具發展潛力、足以替代時下快閃記憶體的潛在競爭者而受到廣泛的矚目。然而，傳統的RRAM僅有高低兩種阻態，在現代記憶體需求下必須耗費大量面積。為了克服這項限制，許多可靠的研究已然證明，RRAM具備了多位元儲存的可能性，藉由此項特性將能達到海量存儲的需求。
    而在眾多半導體材料中，氧化鎵由於其出色的材料特性，做為第四代半導體材料備受期待，常被應用於光電、高功率、電阻開關元件等領域，這一切皆歸因於其高能隙寬度和透明特性。
    而在本文中，我們成功地透過Al/GO/Ga2O3/ITO雙層堆疊結構RRAM實現兩位元存儲的可能性。與單層結構相比，雙層結構具有更加優異的電性和操作穩定性。在開關比超過103的情況下，仍維持著超過100次的開關操作次數。此外，本文也通過阻絲模型以進一步確認介電層中的傳導機制。

    Recently, resistive random access memory (RRAM) has been an outstanding candidate for replacing the metal–oxide–semiconductor flash memory devices. However, the traditional RRAM, which accommodates two states depending on applied voltage, cannot meet the high density requirement in the era of big data. Many research groups have demonstrated that RRAM possesses the possibility of multilevel cell to overcome the demand of mass storage.
    Among numerous semiconductor materials, gallium oxide (Ga2O3), as the fourth-generation semiconductor material, is highly profile due to its excellent material properties, and already is widely used in optoelectronics, high-power, resistive switching device, due to its wide bandgap and transparent properties.
    This paper successfully demonstrates Al/GO/Ga2O3/ITO RRAM to achieve the possibility of two-bit storage. Compared with the monolayer counterpart, the bilayer structure has excellent electrical properties and stable reliability. The endurance characteristics could be enhanced above 100 switching cycles with an On/Off ratio of over 103. The filament models are also described in this thesis to clarify the transmission mechanisms.

    摘要 I Abstract III 誌謝 V Contents VII List of Figures XI Chapter 1 Introduction 1 1.1 Background 1 1.2 Motivation 4 1.3 Organization of the Thesis 7 Chapter 2 Literature Survey 8 2.1 Resistive Random Access Memory 8 2.1.1 Fundamental Definitions 8 2.1.2 Unipolar and Bipolar Modes 10 2.1.3 Resistive Switching Mechanism 11 2.1.4 Conduction Mechanism 13 2.1.4.1 Ohmic Conduction 13 2.1.4.2 Schottky Emission 15 2.1.4.3 Poole-Frenkel Emission 16 2.1.4.4 Tunneling 18 2.1.4.5 Hopping Conduction 21 2.1.4.6 Space-Charge-Limited Conduction 23 2.2 Experimental Materials 25 2.2.1 Gallium Oxide (Ga2O3) 25 2.2.2 Graphene Oxide 28 Chapter 3 Experiment 29 3.1 Fabrication Equipment 29 3.1.1 Spin Coater 29 3.1.2 Oven 30 3.1.3 PVD System 30 3.2 Material Analysis Equipment 33 3.2.1 Raman Spectroscopy 33 3.2.2 X-ray Photoelectron Spectroscopy (XPS) 34 3.2.3 Alpha-Step Profilometer 35 3.2.4 Focused Ion Beam (FIB) 36 3.2.5 Transmission Electron Microscope (TEM) 37 3.2.6 Energy-Dispersive X-ray Spectroscopy (EDS) 39 3.2.7 Spectrophotometer 40 3.2.8 X-ray Diffraction (XRD) 41 3.3 Electrical Analysis Equipment 42 3.3.1 Agilent B1500A 42 3.4 Fabrication Processes 43 3.4.1 Substrate Cleaning 43 3.4.2 Resistive Switching Layer Deposition 44 3.4.2.1 Gallium Oxide Layer Deposition 44 3.4.2.2 Graphene Oxide Layer Deposition 44 3.4.3 Top Electrode Deposition 44 Chapter 4 Results and Discussion 46 4.1 Physical Properties 46 4.1.1 Raman Spectroscopy of GO 46 4.1.2 Bandgap of Ga2O3 film 47 4.1.3 XRD result of Ga2O3 48 4.1.4 TEM image of Device Cross-section 49 4.1.5 Energy Dispersive Spectroscopy Element Analysis 50 4.1.6 Chemical Compositional Analysis 51 4.2 Electrical Properties of Device without GO layer 52 4.2.1 DC IV Characteristics 52 4.2.2 Conduction Mechanism 54 4.2.3 Endurance 57 4.2.4 Data Retention 58 4.2.5 Uniformity 59 4.2.5.1 Cycle-to-cycle Uniformity 59 4.2.5.2 Device-to-device Uniformity 61 4.3 Electrical Properties of Device with GO layer 63 4.3.1 DC IV Characteristics 63 4.3.2 Conduction Mechanism 68 4.3.3 Endurance 71 4.3.4 Data Retention 72 4.3.5 Multi-level Storage 73 4.3.6 Uniformity 76 4.3.6.1 Cycle-to-cycle Uniformity 76 4.3.6.2 Device-to-device Uniformity 83 4.3.7 Pattern Size-dependent Measurement 85 4.3.8 Temperature-dependent Measurement 86 4.4 Comparison between the Devices without/with GO layer 88 Chapter 5 Conclusion 90 Chapter 6 Future Works 92 References 94

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