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| 研究生： |
楊哲彰 Yang, Che-Chang |
|---|---|
| 論文名稱： |
H.264 CABAC編碼器之全硬體設計 A Full Hardware Design for CABAC Encoder of H.264 |
| 指導教授： |
陳培殷
Chen, Pei-Yin |
| 學位類別： |
碩士 Master |
| 系所名稱： |
電機資訊學院 - 資訊工程學系 Department of Computer Science and Information Engineering |
| 論文出版年： | 2007 |
| 畢業學年度： | 95 |
| 語文別： | 英文 |
| 論文頁數： | 34 |
| 中文關鍵詞： | 全硬體 、算術編碼 |
| 外文關鍵詞： | H.264, CABAC, full hardware, encoder, VLSI architecture |
| 相關次數： | 點閱：64 下載：1 |
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H.264/AVC是一個革命性的影像壓縮標準，在H.264 Main Profile中採用了許多先進的編碼技術，其中包括了一組比過往更先進的熵編碼技術：基於上下文的自適應可變長度編碼(CAVLC)/通用可變長度編碼(UVLC)與基於上下文的自適應二進制算術編碼(CABAC)。一般而言，CABAC擁有相對於CAVLC/UVLC更好的壓縮編碼效率，故已成為許多學者研究的主要目標。在本論文中，我們提出了一個能有效管理鄰近區塊資訊的CABAC編碼器全硬體架構設計，在我們的設計中，包括了一個四級管線化架構的BM模組(二進制化和模型化)、一個五級管線化架構的二進制算術編碼器，和其相對應的Packer模組。整個CABAC的VLSI架構以Verilog來實現並使用TSMC 0.13 μm標準元件庫來合成其電路，根據最後的實驗結果，我們提出的CABAC編碼器所需邏輯閘數為19,339，並可達到200MHz的工作時脈。
H.264/MPEG-4 Part 10 Advanced Video Coding is a revolutionary new industry standard video codec. In H.264, the Main Profile enables additional reduction including two novel advanced tools for entropy coding of the bitstream syntax: Universal Variable Length Coding/Context-Based Adaptive Variable Length Coding (UVLC/CAVLC) and Context-Based Adaptive Binary Arithmetic Coding (CABAC). In average, CABAC achieves better bit-rate saving over the VLC entropy coding method (UVLC/CAVLC). In this thesis, we propose a full VLSI hardware design for CABAC encoder system which can manage the neighboring context efficiently. Our design consists of the BM module, the arithmetic coder and corresponding packer where the 4-stage pipelined BM module is used to perform operations of binarization and modeling. The VLSI architecture of our CABAC encoder is implemented with TSMC 0.13 μm technology. It occupies 19,339 gate counts and can work with a clock rate of 200 MHz.
[1] Y. J. Chen, C. H. Tsai, and L. G. Chen, "Analysis and architecture design for multi-symbol arithmetic encoder in H.264/AVC," VLSI Design/CAD Symposium 2005, Aug. 2005.
[2] Y. J. Chen, C. H. Tsai, and L. G. Chen, “Architecture Design of Area-Efficient SRAM-Based Multi-Symbol Arithmetic Encoder in H.264/AVC,” IEEE ISCAS 2006, Page(s):4 pp., May 2006.
[3] Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Team Specification (ITU-T Rec. H.264ISO/IEC 14496-10 AVC).
[4] JVT H.264/AVC Reference Software JM 10.2.
[5] C. C. Kuo and S. F. Lei, “Design of a Low Power Architecture for CABAC Encoder in H.264,” IEEE APCCAS 2006, pp.243-246, 4-7 Dec. 2006.
[6] P. S. Liu, J. W. Chen, and Y. L. Lin, “A Hardwired Context-Based Adaptive Binary Arithmetic Encoder for H.264 Advanced Video Coding,” IEEE VLSI-DAT 2007, pp.1-4, April 2007.
[7] D. Marpe, H. Schwarz, and T. Wiegand, “Context-Based Adaptive Binary Arithmetic Coding in the H.264/AVC Video Compression Standard,” IEEE Trans. Circuits Syst. Video Technol., Vol. 13, no.7, pp.620-636, July 2003.
[8] R. R. Osorio and J.D. Bruguera, “Arithmetic Coding Architecture for H.264/AVC CABAC Compression System,” Euromicro Symposium on Digital System Design, pp. 62-69, 31 Aug.-3 Sept. 2004.
[9] R. R. Osorio and J.D. Bruguera,“ A New Architecture for Fast Arithmetic Coding in H.264 Advanced Video Coder,” Euromicro Symposium on Digital System Design, pp.298-305, 30 Aug.-3 Sept. 2005.
[10] R. R. Osorio and J. D. Bruguera, “High-Throughput Architecture for H.264/AVC CABAC Compression System,” IEEE Trans. Circuits Syst. Video Technol., Vol. 16, Issue 11, pp.1376-1384, Nov. 2006.
[11] H. Shojania and S. Sudharsanan, ”A High Performance CABAC Encoder,” IEEE-NEWCAS Conference, 2005, pp. 104 – 107, June 2005.
校內：2010-08-21公開校外：2010-08-21公開