可變長度編碼是一種常用的無失真壓縮方法。在本論文裡，提出了一個應用在H.264的低成本適應性可變長度編碼方法與其VLSI架構設計。傳統的可變長度編碼法通常需要使用一個相當龐大的字碼表來完成編碼動作。當硬體實現時，為了儲存這樣龐大的表，必須使用到大量的記憶體儲存容量，所以需要相當高的成本。為了降低硬體成本，本論文提出一個新的編碼方法，只需儲存最具代表性的編碼表以及利用一些額外的對應和運算模組來取代傳統的字碼表。所以只需要少量的記憶體空間與簡單的硬體運算模組就可以得到與使用傳統方法一樣的結果。因此我們提出的方法可以大大地降低硬體實現的成本。與過去提出的其它方法比較，我們提出的低成本適應性可變長度編碼法大約可以減少64%到74%的儲存容量。在H.264適應性可變長度編碼的應用上，VLSI架構的設計與實現是使用Artisan TSMC 0.13 標準元件庫來合成其電路。依據合成結果，適應性可變長度編碼器所需的邏輯閘數為11941 gate counts，並可達到400MHz的工作時脈。

Variable-length coding (VLC) is a very popular lossless compression method. In our thesis, we propose a low-cost VLC method and its VLSI architecture for H.264. Traditionally, the VLC method usually needs to use a quite large encoding table to complete the encoding process. When we implement the hardware, in order to store such large tables, we must use an extensive memory capacity, and therefore the cost we need is corresponsive high. To reduce the hardware cost, we propose a novel encoding algorithm which only stores the most representative table and uses some extra mapping and calculating modules to replace the traditional codeword table. Hence, we can obtain the same result with the traditional method by only needing the few memory sizes and the calculating module of the simple hardware. Therefore, the method we propose can greatly reduce the cost of hardware implementation. Compared with the previous methods, the low-cost CAVLC method that we propose can reduce about 64%~74% memory size, and thus need lower hardware cost. For the application of the H.264 CAVLC, the VLSI architecture is designed and implemented by using Artisan TSMC 0.13 cell library. According to the synthesis results, the CAVLC encoder contains 11941 gate counts, and can work with a clock rate of 400 MHz.

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