本論文研製60-GHz COMS低功耗降頻混頻器及應用於單混頻器射頻收發機之可升降頻電阻式環型混頻器毫米波晶片。以上電路皆採用TSMC CMOS 90-nm GUTM 製程進行設計。60-GHz COMS低功耗降頻混頻器採用弱反轉區偏壓技術來達到低功率消耗及低LO功率，IF緩衝放大器採用轉阻放大器來提升整體轉換增益，並藉由轉阻放大器的回授電阻路徑提供mixer core所需的小電流，但不影響轉阻放大器正常操作。依頻率不同設計兩顆可升降頻電阻式環型混頻器，分別為60-GHz CMOS環型混頻器及80-105 GHz CMOS環型混頻器，其混頻的原理為利用電晶體閘極端之電壓變化，達到電晶體等效通道電阻值的改變，進而使輸出訊號為非線性。電路設計部份均使用Agilent ADS與Ansoft 3-D電磁模擬軟體HFSS進行模擬，量測部份則採以on-wafer方式進行量測，並根據所預計量測的特性參數不同，其量測方法與設置亦有所調整。

This thesis presents the research on millimeter-wave (MMW) CMOS low-power down- conversion mixer and up-/down-conversion resistive ring mixer for COMS single mixer RF transceiver, which are implemented by 90-nm GUTM CMOS process. A 60-GHz COMS low-power down-conversion mixer uses weak-inversion bias technique to achieve low-power con- sumption and low LO power excitation, the IF buffer chooses trans-impedance amplifier (TIA) to enhance the total conversion gain. Since the mixer core current is so small, that it can be stolen from TIAs via the feedback resistors. Due to the current of mixer core is very small, the operation of TIAs can maintain normal. For up-/down-conversion resistive ring mixer design, we realized two mixers at different RF bands, which include CMOS ring mixers at 60-GHz and the 80-105 GHz bands. The resistive mixer design principle is using a large gate voltage swing of the transistor to change equivalent channel resistance, and the IF output signal has nonlinear effect. The Agilent ADS and Ansoft three-dimensional (3D) EM simulator HFSS were used for design simulation. The measured performances of the designed MMW CMOS mixer ICs were all performed by using on-wafer measurement. Simulation and measurement results are compared and discussed.

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