本論文利用五環素與本實驗室自行合成之不同烷基駢苯衍生物做為主動層，製作五環素/不同烷基駢苯衍生物十二種有機互補式金屬氧化半導體元件並比較碳數與電性之關係，並且探討有無聚亞醯胺(Polyimide,(PI, Nissan RN-1349))為修飾層對有機互補式金屬氧化半導體的電性差別。首先從X光繞射分析儀去探討烷基駢苯衍生物薄膜成長在聚亞醯胺為修飾層與氧化矽上可得到PTCDI-C9~C13成長在聚亞醯胺為修飾層上發現有其他晶向(002), (003)與 (004)晶向結晶且無序度較小，在原子力顯微鏡下有修飾層時的烷基駢苯衍生物隨著碳數增加表面顆粒越大，導致表面的邊界減少，許多材料分析皆證明著本實驗的有機互補金屬氧化半導體在有修飾層且碳數大於七後烷基駢苯衍生物與五環素有相同的電流與臨界電壓因此有較好的電特性。此外本實驗所製作的有機互補式金屬氧化半導體在沒有聚亞醯胺當修飾層時，五環素與烷基駢苯衍生物表面能與氧化矽差距過大，而無法形成好的晶格與較大的晶粒所以電晶體特性較差，但在主動層與絕緣層之間如有聚亞醯胺修飾時可以製作出提升載子漂移率與電流開關比、降低起始電壓的薄膜電晶體，使其n-type (PTCDI-C7~C13) 與p-type電晶體電特性能相互匹配，並且運用在有機互補式金屬氧化半導體的特性顯著改善，大幅降低消耗功率、增加雜訊邊限能力，並發現烷基駢苯衍生物碳數至七個碳數以前無法得到較好的結晶，因此無法與五環素薄膜電晶體電流匹配，而碳數增加到7以後可從原子力顯微鏡與接觸角等材料分析下可得到較好的晶格大小與表面能的匹配下，因此電流提升到可以跟五環素匹配，而可得較高的邊界雜訊與增益值。
交流量測與穩定度分析下也可得到有機互補式金屬氧化半導體有聚亞醯胺為修飾層可得到較低的延遲時間與穩定的輸出電壓並且可長時間操作下。相反在無聚亞醯胺為修飾層則呈現不穩定的特性。此外有機互補式金屬氧化半導體利用電場應力測試中可得到 n-type 與p-type電晶體電特性經過閘極電場則呈現開關電壓呈現下降趨勢經過500到2000秒下。這反應出聚亞醯胺經過閘極場效內部可分離正負電荷並且使電子與電洞快速被累積在通道上導致開關電壓下降。反應在有機互補式金屬氧化半導體中可得到閘訊邊界比經過場效後依然穩定的沒有改變。
低電壓操作的有機互補式電晶體主要探討以五環素與烷基駢苯衍生物做為半導體層成長在聚亞醯胺為修飾層與氧化鉿絕緣層對有機互補式金屬氧化半導體電特性影響。在五環素與烷基駢苯衍生物做為半導體層成長聚亞醯胺可得到較好的晶向與較大的晶向。因為聚亞醯胺為修飾層其表面能接近於五環素與烷基駢苯衍生物並且有機分子容易擴散在亞醯胺上。在電容對電壓的量測可發現到五環素與烷基駢苯衍生物結構並沒有明顯遲滯現象表示經過聚亞醯胺修飾後電荷進行捕捉與釋放達到一致性。電性上n型與p型電晶體則有較低的開關電壓與較高的開關電流比並且輸出曲線無遲滯現象。此外經由通道長度的調整下可使n型與p型電晶體電流調配一致性。使得有機互補式金屬氧化半導體的特性有較低消耗功率、增加雜訊邊限能力。有機互補式金屬氧化半導體在經由長時間且連續操作下可得到穩定的輸出電壓這反應出此元件具有高穩定度並且可應用在高階電路上。
電晶體穩定度上主要探討連續電流對時間量測，而外加一長期的偏壓於電晶體，會使得累積在通道的電子被半導體與絕緣層介面或是靠近其介面的半導體晶界的深層能態所捕捉，而造成介面產生屏蔽效應以及金屬與半導體層之間的介面產生更多的缺陷，使得其接觸電阻增加，導致電晶體的臨界電壓越往正電壓偏移。然而本實驗室所使用的聚亞醯胺元件修飾層，卻是使電晶體的臨界電壓越變越小。烷基駢苯衍生物做為半導體層，探討半導體層成長在聚亞醯胺（Polyimide, PI, 型號為DA-9000）、聚甲基丙稀酸甲酯（Polymethylmethacrylate, PMMA）與交聯結合的poly（4-vinylohenol）PVP（C-PVP）等修飾層上對電晶體穩定度之影響。經由一萬秒長時間連續對元件操作下可發現到烷基駢苯衍生物成長在聚亞醯胺可得到較高的穩定度並且介面缺陷少於其他兩種修飾層並且反應在開關電壓上。從原子力顯微鏡可發現PMMA表面有過多的孔隙容易造成載子被捕捉造成開關電壓變大。此外交聯結合的C-PVP則是因為容易沒有交聯完全下有-OH groups容易造成電子捕捉。從X光繞射分析儀去探討烷基駢苯衍生物薄膜成長在聚亞醯胺為修飾層有較高的結晶結構與較低的結晶無序度。因為烷基駢苯衍生物的表面極性接近於聚亞醯胺表面因此烷基駢苯衍生物與聚亞醯胺的介面則有較小的缺陷。
有機記憶體元件以五環素有機薄膜電晶體為基礎，導入一高分子薄膜當作電荷捕捉層，結合高介電係數材料氧化鉿薄膜作為其絕緣層，製作成可低操作電壓的有機非揮發性記憶元件。其中使用兩種高分子材料，包括聚乙烯醇（Poly(vinyl alcohol), PVA）與聚甲基丙烯酸甲酯，皆利用溶液旋轉塗佈方式於氧化鉿表面製作薄膜，進而探討兩種不同電荷捕捉層對記憶元件的影響包括寫入/清除速度、記憶窗口、記憶保持能力、與耐久性。當寫入時間較長時，使用PVA當作電荷捕捉層時，其記憶窗口為四種元件中最大，約3.7 V；此外，從原子力顯微鏡圖上發現到PVA薄膜與成長於它之上的五苯環薄膜，其表面相當的粗糙，從表面能上也發現到兩者相當的不匹配，因而推論造成有較多的陷阱能態能捕捉電荷，進而增大其記憶窗口，但PVA薄膜相當的薄，因此對於記憶保持能力與耐久性來說，表現較為不佳。綜合所有能力而言，四種不同電荷捕捉層中最佳的為PMMA，其記憶窗口在經過20 V/1 ms的寫入速度下就有3.1 V的表現，對記憶保持能力而言，經過103 s後，其記憶窗口也只降至2.5 V；重複操作元件40 次後，其記憶窗口並無多大變化，有較佳的耐久性表現。

An organic complementary metal-oxide-semiconductor (O-CMOS) used Pentacene and N,N'-dialkyl-3,4,9,10-perylene tetracarboxylic diimide (PTCDI-Cn, n = 2~13) as active layer. The perylene derivatives were synthesized in our laboratory. In order to modify a SiO2 surface, we used the polyimide (PI, Nissan RN-1349) layer as a modification layer. First, we analyzed the properties of PTCDI films with and without the PI layer by the XRD measurements. The results indicate that the PTCDI-C9~C13 films grown on the PI layer have the obvious (001), (002), (003), and (004) crystalline orientation which are obviously stronger than that the PTCDI films grown on a SiO2. Therefore, the PTCDI-C9~C13 exhibited large crystalline size. AFM images of PTCDI-C7~C13 films exhibited the poly-pillar crystallization. This was interpreted to the fact that the carbon chain of PTCDI-C7~C13 films were enough to form compact poly-pillar crystallization resulting in high molecular packing density. Moreover, the surface morphology of PTCDI-C11~C13 grown on the PI layer were obviously pillars crystallization. This was interpreted to the fact that the surface energy of PTCDI-C6~C13 films were smaller than surface energy the PI layer. Therefore, the molecule of the pentacene and PTCDI films could easily diffuse on the PI layer. The p-type and n-type transistors with the PI layer could reduce leakage current and have similar current resulting in low power dissipation and high noise margin performances of O-CMOS devices. Additionally, both the p-type and n-type transistors using the PI layer had a low subthreshold swing and a high drain current resulting in high gain and great output current of O-CMOS. Then, all of these analysis were point out the PI layer can promote the OTFTs characteristic. Finally, we demonstrated the outstanding O-CMOS characteristics were integrated with PTCDI-C7~C13-based and pentacene-based transistors.
For AC single measurement, PI-modified the O-CMOS devices (pentacene-based and PTCDI-C13-based transistors) with the propagation delay time of 62 s at 1kHz were achieved. The electrical stability of n- and p-type transistors and organic complementary inverters using PI layer of the gate dielectric (silicon oxide, SiO2) was examined. The PI layer reduced the surface defects of SiO2. When the PI layer was inserted into the p- and n-type transistors, the hysteresis and Vt of the devices greatly decreased during gate-bias stress; therefore, the shift of the switching voltage (VS) of the inverters integrated with these p- and n-type transistors was not obvious after bias stress. Moreover, the noise margin high (NMH) and noise margin low (NML) of the inverters with the PI layer under bias stress are stable and superior to those reported in other studies.
Low voltage O-CMOS inverter with the pentacene-based and PTCDI-C13-based transistors using high-k hafnium oxide (HfO2) and the PI hybrid gate-dielectrics were described. The hysteresis of capacitance–voltage measurement for metal-oxide-semiconductor capacitors showed that the PI exhibited high trapping and detrapping speeds for holes and electrons, resulting in low hysteresis of the threshold voltage, and mobility for n- and p-type transistors, respectively. The organic inverter with the PI layer modification layer achieved the low hysteresis of voltage transfer characteristic, low static power dissipation, and high noise margins. Finally, the high level output voltage (VOH) and the low level output voltage (VOL) of the O-CMOS were close to 0 and VDD, respectively under input voltage (VI) = 0 V (VDD = 8 V) and VI = VDD = 8 V, respectively for a stress time of 5000 s.
Studies of time-dependent drain current (ID) continuously performed on devices with different polymeric buffer layers under VGS = VDS = 40 V for 104 s. The time-dependent growth of drain current and nearly hysteresis-free in transistors under dc bias stress was obtained by modifying the SiO2 gate dielectric with PI layer. This was primarily attributed to the reduction of the trap state density located at the interface between the polyimide and organic semiconductor. The OTFTs with the PI and PVP layers had the lower Vt values than that of the OTFTs with the PMMA layer due to the surface energy of PI (36 mJ/m2) and PVP (40 mJ/m2) being similar to that of PTCDI-C13 (32 mJ/m2), which minimized the number of electron traps in the PI/PTCDI-C13, and PVP/PTCDI-C13 interfaces. Higher surface energy (44 mJ/m2) and more cavities in PMMA film contributed higher electron-trap density at the PMMA interface to result in poor performance of PMMA-modified OTFT.
Finally, We demonstrated a simple and inexpensive approach for the low-temperature fabrication (< 200 oC) of low-voltage operated (< 20 V), pentacene-based organic non-volatile memory devices with a high-K hafnium dioxide (HfO2) main dielectric layer and a polymer electret layer. Two kinds of polymer insulators were used as the electret layer, i.e., a polyvinylalcohol (PVA) with strong polar groups and an amorphous poly(methyl methacrylate) (PMMA). Initially, we observed that the devices with the PVA show relative large memory windows than that with the PMMA. However, after long-term retention and multiple continuous writing/erasing cycles and endurance testing, the devices with PMMA showed large and stable memory characteristics. The memory windows in devices with PVA can be attributed to the dominant short-lifetime shallow traps located at the PVA/pentacene interface and in the pentacene film, whereas those in devices with PMMA were mainly due to the long-lifetime deep traps located in the PMMA layer. Based on the surface morphology results, we proposed that the rough interface between PVA/pentacene, strong polar –OH groups on the PVA surface, and more grain boundaries of pentacene films are possible origins of shallow traps, whereas the more free volume vacancies in PMMA films are possible deep trap sites. Accordingly, the devices with the PMMA layer show superior memory characteristics, including a stable memory window of approximately 2.5 V after 20 V 1 s pulse, retains 80% of memory windows after 103 s, and good endurance properties.

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