隨著科技技術快速的發展，人們對於電子產品的要求變得趨向於便利性、低功率消耗以及高操作速度。而在傳統金氧半場效電晶體 (MOSFET) 微小化的過程中會遇到很多元件的特性與製程上難題。為了解決或避免眾多困難點如短通道效應，因此一些新穎的元件陸續的被提出。簡而言之，傳統的平面閘極正被替換為環繞式閘極(gate-all-around)，以改善短通道效應，低截止狀態和高導通狀態電流驅動的晶體體，並擁有更快的開關操作。低漏電流、降低次臨界擺幅和最小化的隨機摻雜波動使得多閘極電晶體成為未來CMOS的重要技術。
在本篇論文中，我們將介紹並討論如何改善環繞式閘極奈米線無接面電晶體(nanowire junctionless transistor)，並且我們利用兩種方式來增加導通電流和減少漏電流。第一個方法是在全Si FET上使用貝殼式摻雜 (shell doping profile)，而另一個方法是使用Si/SiGe SDP FET，在摻雜的部分也就是殼區域中改用不同的材料，利用異質結構(heterojunction) 形成量子井 (quantum well)。本研究通過使用Sentaurus TCAD軟體的模擬結果來實現兩種不同的SDP JLFET，並發現它是未來有發展性的元件，因為它具有兩個主要共同優點：（1）摻雜接近閘極(gate)能擁有較低的漏電流(Ioff)和更好的閘極控制；以及在殼區域中形成量子井能夠將大多數載子限制住，也會有更好的靜電控制能力。（2）與傳統的JLFET和MOSFET相比，SDP JLFET表現出較低的漏電流，以及當奈米線直徑變化時，能擁有差不多的導通電流(Ion)，也就是具有較小的電特性變化。因此，本篇論文所提出的SDP JLFET是極有淺力成為下一個世代的新式元件。

Following technological technique develop rapidly, the requirement of electrical production tend to convenient, low power consumption, high speed velocity. There will cause many difficult problems of manufacture process and device characteristic when scale down traditional MOSFET. In order to avoid nonideal phenomenon, some novel devices are presented continually. In short, conventional planar-gate is being replaced with gate-around-gate to realize transistors with better short channel effects, low off-state and high on-state current drive which allows faster switching operation. Low drain voltage, reduced swing in threshold voltage and minimized random dopant fluctuations made multi-gate transistors suitable candidate for future CMOS technologies.
In this thesis, we will discuss how to improve gate-all-around nanowire junctionless transistor and we utilize two ways to increase ON-current and decrease OFF-current. The one is using shell doping profile on a Full-Si FET and another one is to using quantum well by heterostructure on a Si/SiGe SDP FET. SDP nanawire JLT is a promising device in the future due to it possesses two main advantages: (1) the dopant proximity to the gate guarantees a lower OFF-current and a better gate control, and a quantum well in the shell region for the majority carriers leads to a better electrostatic control by confining the carriers. (2) Compared with the traditional JLFETs and MOSFETs, SDP-JLFETs exhibit lower OFF-current by decades and less electrical characteristics variation resulting from the diameter variation as their ON-currents saturate at a similar level.
Our device can be supported by simulated results using technology computer-aided design (TCAD) simulation. According to the results of the research, the novel SDP JLFET shows superior potential for the future device.

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