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研究生: 朱家毅
Chu, Chia-Yi
論文名稱: 以切割字串為基礎之字串比對的管線化架構
Pipeline Architecture for Segmented Pattern Matching
指導教授: 張燕光
Chang, Yeim-Kuau
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Department of Computer Science and Information Engineering
論文出版年: 2014
畢業學年度: 102
語文別: 英文
論文頁數: 49
中文關鍵詞: FPGA字串比對管線化設計
外文關鍵詞: FPGA, Pattern matching, Pipeline
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  • 在近幾年內,隨著網路流量快速的增加,以深度封包檢測系統 (Deep packet inspection, DPI) 來確保資訊安全的需求變得越來越重要。深度封包檢測系統依靠著字串比對來檢測封包的內容,來尋找封包內可能的威脅。所以字串比對的效能就是深度封包檢測系統的一個關鍵點。我們必須去找出一個能有穩定效能且低記憶體需求的演算法,去改進字串比對的效能。為了使知名的Aho-Corasick (AC) 演算法能運行在管線化架構上,我們將字串切割成許多子字串,避免產生過多線程且能同時在輸入流中同時運行。在這篇論文中,我們提出一個能在字串集合中尋找出所有共同子字串的方法並且利用這些共同子字串去切割原本的字串。在切割字串集合後,我們用這些得到的子字串去建立AC-DFA,且因為是運行在管線化架構上, 此AC-DFA中所有的failure transition可被移除。之後為了將這些子字串再次組合成原本的字串,我們使用了一個樹狀的資料結構將AC-DFA的結果再次結合成原本尚未切割的字串。在最後,我們利用這兩個資料結構的transition表格建立我們的管線化架構。我們的實驗結果顯示,在子字串分組值K為5,處理約58,000字元的時候,我們利用了Xilinx Virtex-7 XC7V2000T上約5.9%的Block RAM、0.2%的Slice Registers以及16%的Slice LUTs。在記憶體消耗量上比Split AC及Bit-Split分別少了29%及75%。

    In recent years, due to the rapid growth of network traffic, the demand of deep packet inspection (DPI) system to ensure the network security is becoming more and more important. The DPI systems rely on pattern matching to detect the payload of the packet, in order to find possible threats in the packet. Therefore, the performance of pattern matching is the key point of the DPI systems. We have to figure out a solution that provides stable throughput and has low memory requirement to improve the performance of pattern matching. In order to let the well-known Aho-Corasick (AC) algorithm work on the pipeline architecture, we segment the patterns into pattern segments for decreasing the number of threads that tracks the input stream. In this thesis, we propose a technique to find out all the common subpatterns in the pattern set and use them to divide the patterns. After dividing the patterns, we use the pattern segments to build up the AC-DFA that eliminates all the failure transitions that are not needed in the pipeline architecture. In addition, we have to combine the subpatterns into their original pattern. Here, a tree-like structure is used for AC-DFA without failure transitions to find the original patterns. Finally, we use the transition tables of these two structures to construct the pipeline architecture. Our implementation result shows that on Xilinx Virtex-7 XC7V2000T, when group threshold K = 5, which handles 58k characters, we utilize 5.9% of Block RAM, 0.2% of Slice Registers, and 16% of Slice LUTs. The memory cost of our scheme is lower than Split AC and Bit-split by 29% and 75%.

    Chapter 1 Introducion 1 1.1 Introduction 1 1.2 Organiztion of the thesis 3 Chapter 2 Related Works 4 2.1 Real-life open source DPI systems 4 2.1.1 ClamAV 4 2.1.2 Snort 5 2.2 Aho-Corasick Algorithm 5 2.3 P2-AC 7 2.4 Prasanna’s scheme 10 2.5 Multi-core processor-Based 13 2.6 TCAM-Based 14 2.7 FPGA-Based 15 2.8 Other Pattern Matching approaches 17 Chapter 3 Proposed Scheme 18 3.1 Motivation 18 3.2 Common Subpatterns 19 3.3 Segment AC (SAC) and Agrregation tree (AT) 26 3.4 The Hardware Architecture 32 Chapter 4 Performance Evaluation 38 4.1 Analysis of Real-life Pattern Sets 38 4.2 Analysis of our proposed scheme 40 Chapter 5 Conclution 46 Reference 47

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