近年來，中值濾波器的應用越來越多了，不管是在音訊上或者是在影像上的應用，最經典就是去除椒鹽雜訊，因為不管是影像或者是音訊皆可能會有椒鹽雜訊產生，
而本文主要在討論用於影像除雜訊相關的中值濾波器設計。
因為影像具有二維特性，本文主要討論”二維中值濾波器”，使用二維中值濾器對影像進行處理，相較於用傳統的”一維中值濾波器”進行影像處理可以減少輸入與輸出時不必要的時序延遲，可使每個時序的中值輸出皆為有效的輸出，可以增加濾波器的
產出。
在去除椒鹽雜訊的應用時使用不同的sliding window大小的中值濾波器處理會有不同的結果，sliding window較大可以去除較多雜訊，sliding window較小可以減少模糊，可以依照需求做選擇，本文提出一種可適用各種大小sliding window的中值濾波器設計方法，並實作了 3*3, 5*5 ,7*7 ,三種不同sliding window大小的中值濾波器，而且因為此架構可以平行處理及 pipeline ，三種不同sliding window大小都可以達到real-time的處理速度。
本文設計了讓部分元件重複使用的方法，使架構在3*3、5*5、7*7的sliding window下，在相同產出量下，皆比其他paper所提出的架構在的成本都還要少，並且同時具備不低於其他paper架構的工作效率。
所有的電路都是使用Verilog 硬體描述語言來實作，以SYNOPSYS Design Compiler及Artisan TSMC 90nm標準元件庫進行合成，該電路在3*3 Sliding Windows ，8bit資料，1倍產出時，僅需要4931um2的面積，工作時脈可以達到2000MHz，吞吐量(throughputs)則為每秒2000x106個中值，平均每秒可以處理305張(3200×2048)大小的
畫面。與其他電路實作的論文相比，本文的電路成本較低且能在相同或較短的時間內處理完一張圖片。

In recent years, the application of the median filter has been increasing. Whether it is in the application of audio or video, the most classic is to remove the salt and pepper noise, because both of them may cause salt and pepper noise for several reasons. This article mainly discusses the design of median filter for image noise removal.
In order to meet the two-dimensional property of the image, this article mainly discusses the "two-dimensional median filter". Instead of 1D median filter, using 2D median filter for image process can reduce the unnecessary timing delay with output and input. We can improve the throughput of the filter.
In the application of removing salt and pepper noise, the use of different sliding window sizes will have different results. A larger sliding window can remove more noise, a smaller sliding window can reduce blurring. This paper proposes a median filter design method applicable to various sizes sliding windows, and implements median filters with 3*3, 5*5, 7*7 sliding window. Because this architecture can be parallel processing and pipeline, all median of three different sizes can achieve real-time processing speed.
This paper present a method to reuse some of the unit. So the circuit need lower cost than other proposed under the same throughput and sliding window size.
All circuits are implemented using Verilog hardware description language, and synthesized by SYNOPSYS Design Compiler and Artisan TSMC 90nm standard cell library. This design in 3*3 sliding window, 8bit data, and 1 throughput per cycle only require the area is 4931 um2 . The working frequency is 2000MHZ, and produce 2000*106 medians per second, in other word it can process 305 frames which image size is 3200*2048 per cycle. Compare with other paper proposed, need lower cost and process a picture in the same or shorter time.

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