| 研究生: |
黃兆麟 Huang, Jhao-Lin |
|---|---|
| 論文名稱: |
陷阱電荷對RF鰭式電晶體的影響之探討 Study of the impact of traps on RF FinFETs |
| 指導教授: |
江孟學
Chiang, Meng-Hsueh |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 奈米積體電路工程碩士博士學位學程 MS Degree/Ph.D. Program on Nano-Integrated-Circuit Engineering |
| 論文出版年: | 2021 |
| 畢業學年度: | 109 |
| 語文別: | 英文 |
| 論文頁數: | 39 |
| 中文關鍵詞: | 鰭式場效電晶體 、TCAD 、射頻 、特性值 、寄生電容 、閘極電阻 |
| 外文關鍵詞: | FinFET, TCAD, RF, Figure of Merit, Parasitic Capacitance, Gate Resistance |
| 相關次數: | 點閱:96 下載:0 |
| 分享至: |
| 查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
隨著製程技術的進步,鰭式場效電晶體已然成為主流的元件。因為鰭式場效電晶體屬於3D結構,故運用在射頻表現極度與鰭式場效電晶體的結構尺寸有關。電晶體的微縮隨時間不斷推進,須考量的寄生元件的影響會變得顯著,勢必會影響到鰭式場效電晶體的射頻表現。例如:截止頻率於閘極長度縮減時,應該會與閘極長度平方的倒數成正比,但寄生元件的存在使得截止頻率僅與閘極長度倒數成正比。
在該篇論文中,我們將討論到鰭式場效電晶體的尺寸如何改變寄生元件與射頻表現。尤其於實際製程,因為是非理想情況,使得製造電晶體的過程中會產生些許陷阱電荷衰減直流特性與交流特性。因此,利用TCAD軟體模擬的方式,旨在比較當固定電晶體尺寸時,陷阱電荷的濃度多寡會對寄生元件與射頻表現產生多大影響,以做為未來設計射頻元件時的參考。
With the advance of the process, FinFET has been a mainstream device. Because FinFET is the 3D geometry, it extremely depends on the size of the structure in the RF performance. When we continue scaling devices, the effects of the parasitic components we concerned become more significant, and those parasitic components must impact on the RF performance of FinFET. For example, the cut-off frequency should be proportional to 1/Lg2 when the gate length is reduced, but it only is proportional to 1/Lg due to the presence of parasitic components.
In this thesis, we will discuss how the size of the FinFET changes the parasitic components and the RF performance. Especially for the actual process, it produces some trap charges to attenuate both dc characteristics and ac characteristics when manufacturing transistors since it is in a nonideal situation. Therefore, we focus on how the trap charge concentration impacts on the parasitic components and the RF performance by using the TCAD simulation if the size of the transistor is fixed, and it can be a reference for design the RF devices in the future.
[1] Gordon E. Moore, “Cramming more components onto integrated circuits” Proceedings of the IEEE, Vol.86, pp. 82-85, 1998.
[2] J. Singh et al., “14nm FinFET Technology for Analog and RF Applications,” in 2017 Symposium on VLSI Technology, pp. T140–T141, June 2017.
[3] INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS ™ 2020 UPDATE.
[4] V. Subramanian, B. Parvais, J. Borremans, A. Mercha, D. Linten, P.Wambacq, J. Loo, M.Dehan, C. Gustin, N. Collaert, S. Kubicek, R. Lander, J.Hooker, F. Cubaynes, S. Donnay, M. Jurczak, G. Groeseneken, W. Sansen, and S. Decoutere, “Planar Bulk MOSFETS Versus FinFETs: An Analog/RF Perspective”, IEEE Transactions on Electron Devices, Vol. 53, no. 12, pp. 3071-3079, December 2006.
[5] Lee, H.-J., S. Rami, S. Ravikumar, V. Neeli, K. Phoa, B. Sell, and Y. Zhang, “Intel 22 nm FinFET (22FFL) process technology for RF and mm Wave applications and circuit design optimization for FinFET technology,” in International Electron Devices Meeting (IEDM 2018), 14.1.1–14.1.4, San Francisco, CA, USA, December 2018. [6] C. R. Manoj, Meenakshi Nagpal, Dhanya Varghese, and V. Ramgopal Rao “Device Design and Optimization Considerations for Bulk FinFETs” IEEE Transactions on Electron Devices, Vol. 55, no. 2, February 2008.
[7] Wen Wu and Mansun Chan, “Analysis of geometry-dependent parasitics in multifin double-gate FinFETs,” IEEE Transactions on Electron Devices, Vol. 54, no. 4, pp. 692-698, April 2007.
[8] S. Salas, J. C. Tinoco, A. G. Martinez-Lopez, J. Alvarado and J.-P. Raskin, “Parasitic Gate Capacitance Model for Triple-Gate FinFETs”, IEEE Transactions on Electron Devices, Vol. 60, no. 11, pp. 3710-3717, November 2013.
[9] S. Salas, J. C. Tinoco, A. G. Martinez-Lopez, J. Alvarado, and J.-P. Raskin, “Fringing gate capacitance model for triple-gate FinFET,” in 13th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE, pp. 90-92, January 2013.
[10] Lee, K.; An, T.; Joo, S.; Kwon, K.-W.; Kim, S., "Modeling of Parasitic Fringing Capacitance in Multifin Trigate FinFETs," IEEE Transactions on Electron Devices, Vol.60, no.5, pp. 1786-1789, May 2013.
[11] R. Shrivastava and K. Fitzpatrick, “A simple model for the overlap capacitance of a VLSI MOS device,” IEEE Transactions on Electron Devices, Vol. ED-29, p.p. 1870-1875, 1982.
[12] V. Subramanian et al., "Identifying the bottlenecks to the RF performance of FinFETs," in International Conference on VLSI Design, pp. 111-116, January 2010.
[13] I. Kwon, M. Je, K. Lee, and H. Shin, "A simple and analytical parameter extraction method of MOSFET for microwave modeling," IEEE Transactions on Microwave Theory and Techniques, Vol. 50, no. 6, pp. 1503-1509, June 2002.
[14] Y. S. Chauhan, D. D. Lu, V. Sriramkumar, S. Khandelwal, J. P. Duarte, N. Payvadosi, A. Niknejad, and C. Hu, FinFET Modeling for IC Simulation and Design: Using the BSIM-CMG Standard. San Diego, CA, USA: Academic, 2015.
[15] J.-P. Raskin, “FinFET and UTBB for RF SOI communication systems,” Solid-State Electron., Vol. 125, pp. 73–81, November 2016.
[16] Synopsys. “SentaurusTM Structure Editor User Guide”, Version L-2016.03, March 2016.
[17] Synopsys. “SentaurusTM Device User Guide”, Version L-2016.03, March 2016.
[18] S. M. Sze and M.-K. Lee, Semiconductor Devices: Physics and Technology. Hoboken, NJ, USA: Wiley, 2012.
校內:2026-08-01公開