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研究生: 黃兆麟
Huang, Jhao-Lin
論文名稱: 陷阱電荷對RF鰭式電晶體的影響之探討
Study of the impact of traps on RF FinFETs
指導教授: 江孟學
Chiang, Meng-Hsueh
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 奈米積體電路工程碩士博士學位學程
MS Degree/Ph.D. Program on Nano-Integrated-Circuit Engineering
論文出版年: 2021
畢業學年度: 109
語文別: 英文
論文頁數: 39
中文關鍵詞: 鰭式場效電晶體TCAD射頻特性值寄生電容閘極電阻
外文關鍵詞: FinFET, TCAD, RF, Figure of Merit, Parasitic Capacitance, Gate Resistance
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  • 隨著製程技術的進步,鰭式場效電晶體已然成為主流的元件。因為鰭式場效電晶體屬於3D結構,故運用在射頻表現極度與鰭式場效電晶體的結構尺寸有關。電晶體的微縮隨時間不斷推進,須考量的寄生元件的影響會變得顯著,勢必會影響到鰭式場效電晶體的射頻表現。例如:截止頻率於閘極長度縮減時,應該會與閘極長度平方的倒數成正比,但寄生元件的存在使得截止頻率僅與閘極長度倒數成正比。
    在該篇論文中,我們將討論到鰭式場效電晶體的尺寸如何改變寄生元件與射頻表現。尤其於實際製程,因為是非理想情況,使得製造電晶體的過程中會產生些許陷阱電荷衰減直流特性與交流特性。因此,利用TCAD軟體模擬的方式,旨在比較當固定電晶體尺寸時,陷阱電荷的濃度多寡會對寄生元件與射頻表現產生多大影響,以做為未來設計射頻元件時的參考。

    With the advance of the process, FinFET has been a mainstream device. Because FinFET is the 3D geometry, it extremely depends on the size of the structure in the RF performance. When we continue scaling devices, the effects of the parasitic components we concerned become more significant, and those parasitic components must impact on the RF performance of FinFET. For example, the cut-off frequency should be proportional to 1/Lg2 when the gate length is reduced, but it only is proportional to 1/Lg due to the presence of parasitic components.
    In this thesis, we will discuss how the size of the FinFET changes the parasitic components and the RF performance. Especially for the actual process, it produces some trap charges to attenuate both dc characteristics and ac characteristics when manufacturing transistors since it is in a nonideal situation. Therefore, we focus on how the trap charge concentration impacts on the parasitic components and the RF performance by using the TCAD simulation if the size of the transistor is fixed, and it can be a reference for design the RF devices in the future.

    摘要 I Abstract II Contents VI Table Captions VII Figure Captions VIII Chapter 1 Introduction 1 1.1 Background 1 1.2 Motivation 2 1.3 Introduction of Simulation Tools 3 1.4 Overview of the Thesis 4 Chapter 2 Review of RF Characteristic for FinFET 5 2.1 FinFET Structure 5 2.2 Bulk and SOI FinFET 7 2.3 Parasitic Parameter 8 2.3.1 Parasitic Capacitance 8 2.3.2 Gate Resistance 11 2.3.3 S/D Series Resistance 13 2.4 Figure of Merit 14 2.4.1 Ft 16 2.4.2 Fmax 18 Chapter 3 Device Design and Simulation 19 3.1 Device Design 19 3.2 Simulation Model Used in the Device [16] 21 3.3 Impact of Modification on FoM 21 3.3.1 Effect of the Fin Spacer 21 3.3.2 Effect of the Fin Width 23 Chapter 4 Simulation for Including Fixed Traps 26 4.1 Trap in the Oxide Layer 26 4.2 Effect of the Different Trap Concentration 28 4.2.1 The Fin Spacer 28 4.2.2 The Fin Width 32 Chapter 5 Conclusion 36 References 38

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