為滿足消費性電子輕量化、高性能的需求，在製程封裝上必須將同等晶片面積內I/O數量提升或縮小晶片體積。而封裝逐漸微型化，傳統的錫球凸塊容易造成短路，已難以使用在更精細封裝上。而短路的問題在銅柱凸塊發展後獲得了改善，而銅柱凸塊亦具有更佳的導熱性、導電性及抗電子遷移功能。
本文主要利用ANSYS Workbench進行模擬，先將封裝體模型建立並設定各元件材料參數及模型之邊界條件，接著再將模型施予-40~125的溫度循環負載。其中凸塊焊錫與底部錫球為非線性黏塑性材料，因此選用亞蘭德模型來描述其黏速性行為。最後觀察構裝體的應變分布以及凸塊焊錫在溫度循環過程中的等效塑性應變變化(Equivalent plastic strain range)，並將結果代入Coffin-Manson疲勞壽命預測公式來探討凸塊焊錫的可靠度。
在結果與討論中，針對封裝體進行參數最佳化設計，首先一次僅改變一個因子進行分析，以了解各因子水準的變動對於封裝體可靠度的影響，發現焊錫高度與ABF熱膨脹係數為影響較大的因子，最後再利用田口氏品質設計法中直交表及變異分析，求得最佳的參數組合，接著與原始設計參數進行比較，其疲勞壽命提升42%，因此對封裝體之可靠度提升有顯著的效果。

In order to meet the demand for lightweight and high performance of consumer electronics, the number of I/Os in the same wafer area must be increased or reduce the wafer volume.As the package is gradually miniaturized, conventional solder ball bumps are prone to short circuits, making it difficult to use on finer packages.However,the problem of short circuit is improved after the development of copper stud bumps, and the copper stud bumps also have better thermal conductivity, electrical conductivity and anti-electron migration.
This paper mainly uses Ansys Workbench to simulate, first establish and set the material parameters of the package and the boundary conditions of the model, and then apply the model to the temperature cycle load of -40 °C ~ 125 °C.Among them, the bump solder and the bottom solder ball are nonlinear viscoplastic materials, so the Anand's model is used to describe the viscoplastic behavior.Finally, the strain distribution of the structure and the equivalent plastic strain change of the bump solder during the temperature cycling were observed, and the results were substituted into the Coffin-Manson formula to investigate the reliability of the bump solder.
In the results, i focus on the parameter optimization design of the package.First, only one factor is changed at a time for analysis to understand the impact of changes in each factor level on packages' reliability. It was found that the solder height and the ABF thermal expansion coefficient are factors that have a large influence.Finally, using the arthogonal arrays and analysis of variance in the Taguchi method, the best parameter combination is obtained, then compared with the original design parameters, the fatigue life is increased by 42%, so the reliability of the package is significantly improved.

[1]Lee, S.W.R., Lau, D., “Computational Model Validation with Experimental
Data from Temperature Cycling Tests of PBGA Assemblies for the Analysis of Board Level Solder Joint Reliability," 5th International Conference on Thermal and Mechanical Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2004, pp. 115-120, 2004 .
[2] H. C. Tsai, W. R. Jong and S. H. Peng, "The Comparison of IC Packages
with/without Underfill of the Thermo-Mechanical Characteristics",
pp.1444-1448, ANTEC, 2007
[3]W. W. Lee, L. T. Nguyen and G. S. Selvaduray, "Solder Joint Fatigue Models:
Review and Applicability to Chip Scale Packages", Microelectronics and
Reliability, Vol. 40, pp.231-244, 2000
[4]D. H. Kim, P. Elenius and S. Barrett, "Solder Joint Reliability and
Characteristics of Deformation and Crack Growth of Sn-Ag-Cu Versus
Eutectic Sn-Pb on a WLP in a Thermal Cycling Test", IEEE Transactions on
Electronics Packaging Manufacturing, Vol. 25, No. 2, April 2002
[5]Haiyu, Q., Ganesan, S., Osterman, M. and Pecht, M., "Accelerated Testing and Finite Element Analysis of PBGA Under Multiple Environmental Loadings", 2004 International Conference on the Business of Electronic Product Reliability and Liability, pp. 99-106, 2004.
[6]Shin-Hua Chao, Chih-Ping Hung, Mark Chen, Youru Lee, Joey Huang, Golden Kaoa, Ding-Bang Luh. “An embedded trace FCCSP substrate without glass cloth", MICROELECTRONICS RELIABILITY, Vol. 57, pp. 101-110
[7] Nusrat J. Chhanda, Jeffrey C. Suhling, Pradeep Lall, “Effects of moisture exposure on the mechanical behavior of flip chip underfills in microelectronic packaging", IEEE Thermal and Thermomechanical Phenomena in Electronic Systems, pp.333-345,2014.
[8]Zane E. Johnson , "A Compilation of Anand Parameters for Selected SnPb and Pb-free Solder Alloys"
[9] 邱美玲/譯, "先進半導體構裝用模封材料技術動向", 機械月刊第三十四卷第十期, P110-P122, October 2008.
[10] ANSYS Menu, “Newton-Raphson Procedure", ANSYS Theory Reference, Reversion 5.5, pp.15-28-40, 1998.
[11] Anand, L., " Constitutive Equations for the Rate-Dependent Deformation of Metals at Elevated Temperatures", Transactions of The ASME. Vol.104, pp.12-17, 1982.
[12]Darveaux, R., " Effect of Simulation Methodology on Solder Joint Crack Growth Correlation", Journal of Electronic Packaging, Vol. 124(3), pp. 147-154, 2000.
[13]M. Amagai, M. Watanabe , M. Omiya, K. Kishimoto, T. Shibuya, “Mechanical characterization of Sn–Ag-based lead-free solders", Microelectronics Reliability, Vol.42, pp.951-966, 2002.
[14] J. Zhu, “Effects of Anchor Pads in Micro-Scale BGA", IEEE Electronic Components and Technology Conference, pp. 1731-1736, 2000.
[15] B. Rodgers, B. Flood, J. Punch, F. Waldron, “Experimental Determinatioio and Finite Element Model Validation of the Anand Viscoplasticity Model Constants for SnAgCu", IEEE Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, pp. 490 – 496, 2005.
[16] W.W. Lee, L.T. Nguyen, G.S. Selvaduray, “ Solder joint fatigue model: review and applicability to chip scale packages", Microelectronics Reliability, Vol.40, pp.231-244, 2000.
[17] Coffin, L. F., “Fatigue at High Temperature", Fatigue at Elevated Temperature , ASTM STP 520, American Society for Testing and Materials, pp. 5-34, 1973.
[18] Manson, S. S., “Thermal Stress and Low Cycle Fatigue", McGraw-Hill, New York , 1966.
[19] H.D. Solomon, “Low-Cycle Fatigue of 60Sn/40Pb Solder", ASTM Special Technical Publication, Philadelphia, Pa, USA, pp. 342-370, 1985.
[20] E.C. Cutiongco, S. Vaynman, M.E. Fine, and D.A. Jeannotte, “Isothermal Fatigue of 63Sn-37Pb Solder", Journal of Electronic Packaging, Vol.112, pp.110-114, 1990.
[21] W. Engelmaier, “Fatigue Life of Leadless Chip Carrier Solder Joints During Power Cycling," IEEE Transactions on Components, Hybrids and Manufacturing Technology, Vol. CHMT-6, No. 3, pp. 52-57, 1983.
[22] H.D. Solomon, “Fatigue of 60/40 Solder," IEEE Transactions on Components, Hybrids and Manufacturing Technology, Vol. CHMT-9, No. 4, pp.423-431, 1986.
[23] J. P. Clech, “BGA, Flip-Chip and CSP Solder Joint Reliability: of the Importance of Model Validation", InterPack, pp.112-121, 1999.
[24] J.H.L. Pang, P.T.H. Low, B.S. Xiong, “Lead-free 95.5Sn-3.8Ag-0.7Cu Solder Joint Reliability Analysis For Micro-BGA Assembly", IEEE Thermal and Thermomechanical Phenomena in Electronic Systems, Vol.2, pp.131-136, 2004.
[25] T. Takahashi, S. Hioki, I. Shohji, O. Kamiya, “Fatigue Damage Evaluation by Surface Feature for Sn–3.5Ag and Sn–0.7Cu Solders", Materials Transactions, Vol. 46, No. 11, pp. 2335-2343, 2005.
[26] C. Kanchanomai, Y. Miyashita, and Y. Mutoh, “Low-Cycle Fatigue Behavior of Sn-Ag, Sn-Ag-Cu, and Sn-Ag-Cu-Bi Lead-Free Solders", Journal of ELECTRONIC MATERIALS, Vol. 31, No. 5, pp. 456-465, 2002.
[27]李輝煌,“田口方法品質設計的原理與實務",高立圖書, 2011.
[28]John H. Lau, “Recent Advances and New Trends in Flip Chip Technology", Journal of Electronic Vol.138(3),2016.
[29] Lau, J. H., and Pao, Y., 1997, Solder Joint Reliability of BGA, CSP, and Flip Chip Assemblies, McGraw-Hill, New York.
[30] Chaosuan Kanchanomai, Yukio Miyashita, Yoshiharu Mutoh, “Low-Cycle Fatigue Behavior of Sn-Ag, Sn-Ag-Cu, and Sn-Ag-Cu-Bi Lead-Free Solders", Journal of Electronic Materials, Volume 31, Issue 5, pp 456–465,2002.
[31]Release 15.0 Documentation for ANSYS, “Element Library-Solid186", ANSYS Mechanical APDL Element Reference, 2013.
[32] Temperature Cycling, “JESD22 A104-D", JEDEC, 2009.
[33] Yong-Hyuk Kwon, Hee-Seon Bang, and Han-Sur Bang, “Viscoplasticity Behavior of a Solder Joint on a Drilled Cu Pillar Bump Under Thermal Cycling Using FEA", Journal of Electronic Materials, Vol.46, Issue 2, pp 833–840,2007.
[34] Dominik Herkommer, Jeff Punch, Michael Reid, “A reliability model for SAC solder covering isothermal mechanical cycling and thermal cycling conditions", Microelectronics Reliability, Vol.50, Issue 1, Pages 116-126,2010
[35] M. Pei and J. Qu, “Constitutive Modeling of Lead-Free Solders" , IEEE Advanced Packaging Materials: Processes, Properties and Interfaces, pp.45-49, 2005.
[36] Masazumi Amagai, “Characterization of chip scale packageing materials", IEMT/IMC Symposium 2nd pp.216~223,1998