半導體產業已發展相當久的時間，晶圓大小也由四吋一直到現在的十二吋，晶圓尺寸越做越大，積體電路線寬越做越小，而晶片面積越小，晶圓可生產的晶片數越多，這也代表著製程技術面對到相當大的挑戰，在晶圓製程過程中，薄膜製程膜厚度的掌控與蝕刻製程後的副產物殘留，均會影響晶圓良率，尤其是晶圓外圈良率，晶圓良率在晶圓代工產業是一項非常重要的指標，因為良率的高或低會直接影響晶圓售價，所以晶圓外圈良率的製程改善與提升成為研究重點之一。
本論文即在探討，晶圓晶邊可能造成缺陷(Defect)的來源，形成缺陷的情況相當多，包含製程材料的改變和薄膜製程的膜累積與蝕刻製程副產物等。
使用晶邊蝕刻技術(Bevel Etch)，將晶邊薄膜製程的膜累積與蝕刻製程副產物去除，減少晶邊的缺陷，而提升晶圓外圈良率提升，同時考慮晶邊蝕刻技術製程Q-Time，避免晶圓的報廢。
實驗結果顯示，加入晶邊蝕刻製程後，晶圓晶邊有相大幅度的改善，晶邊表面變的平坦結構也相當的穩固，而外圈良率也比未加入晶邊蝕刻的產品良率高，外圈良率提升16.5%，達到實驗預期的結果。

The yield of a large wafer with a smaller feature size can be grossly divided into two zones: the margin and the inner zones. The remarkable development in etching provides users to perform etching with increasing etching depth. However, etching also produces more by-products and lowers etching quality in the marginal zone of the wafer which in turn reduces the overall yield of the wafer and requires close attentions and motivates this study.
In this study, defects caused by wafer bevel were observed and analyzed for the possible causes. The change of materials, film accumulation, and etching by-products were all possible causes which result in defects in the margin zone and influence the yield subsequently.
By using a novel wafer bevel etch, deposited impurities and etching by-products could be removed before the development of defects in the subsequent processes. By flatting the surface of wafer-edge through bevel etch, the wafer edge defects could be reduced to improve the yield of the margin zone. However, in using bevel etching, one must pay attention to the process Q-time to avoid wafer scrap.
The experimental results show that, after adding bevel etch, the quality of the wafer bevel is greatly improved; the surface of the wafer bevel is becoming flat and the structure is quite stable. The yield of the margin zone of wafers is higher than the product without bevel etching. The margin zone quality can be improved up to 16.5%, reaching the expected results of the experiment

[1] Scott Hiemke, Ali Bousetta , “In-line partial die inspection methodology for edge yield improvement” , ISMI Symposium on Manufacturing Effectiveness, Session 9, October 11, 2006.
[2] T. Le, Rudolph Technologies, “Monitoring immersion-based wafer-edge defects”, Semiconductor International, pp. 1-4, April, 2007
[3] Hajime Ugajin, Hayato Iwamoto, Eiji Hide, Nobuyasu Hiraoka, Tsuyoshi Okumura, “New Brush Scrubbing Techniques for a Wafer Bevel, Apex and Edge”, Solid State Phenomena, Vol. 134, pp. 205-208, 2008.
[4] B. Smith, H. Kang, A. Bourov, F. Cropanese, Y. Fam, “Wafer Immeraion Optical Lithography for the 45nm Node,” Proc. SPIE, Vol. 5040, pp. 679-689, 2003.
[5] M. Kocsis, Dieter Van Den Heuvel, Roel Gronheid, Mireille Maenhoudt, Dizana Vangoidsenhoven, Greg Wells, Nickolay Stepanenko, Michael Benndorf, Hyun Woo Kim, Shinji Kishimura, Monique Ercken, Frieda Van Roey, S. O'Brien, Wim Fyen, Philippe Foubert, Richard Moerman and Bob Streefkerk, “Immersion-specific Defect Mechanisms: Findings and Recommendations for Their Control, Proc. SPIE, Vol. 6154, pp. 154-180, 2006.
[6] F. Burkeen, S. Vedula, S. Meeks , “Visualizing the wafer's edge” , KLA-Tencor Yield Management Solutions Magazine , Winter , 2007.
[7] Alan Carlsona, Tuan Lea, Ajay Paia, Joseph Hallenb, Bridget Riouxb, “Use of automated EBR metrology inspection to optimize the edge bead process”, SPIE Advanced Lithography, February, 2007.
[8] Ronnie Porat, Kfir Dotan, Shirley Hemar, Lior Levin, Chen-Ting Lin, Sheng-Kuo Lin, Hsin-I Wang, “SEM-based methodology for root cause analysis of wafer edge and bevel defects”, Advanced Semiconductor Manufacturing Conference, IEEE/SEMI, pp. 11-14, May, 2008 (ISBN 978-1-4244-1964-7)
[9] Taiki Murata, Masayuki Sato, “Reduction of wafer edge induced defect by WEE optimization, ISSM Paper: YE-P-230, IEEE, 2007.
[10] Tong Fang, Yunsang Kim, Keechan Kim, George Stojakovic, “ Control of Bevel Etch Film Profile Using Plasma Exclusion Zone Rings Larger than the Wafer Diameter”, US Patent, September 17, 2009.
[11] Tong Fang, Yunsang Kim, Andreas, “High Pressure Bevel Etch Process”, US Patent, July 8, 2010.
[12] Yunsang Kim, Andrew Bailey, Iii, Jack Chen, “Low-K Damage Avoidance During Bevel Etch Process”, US Patent, July 15, 2010.
[13] V. Vahedi, M. Srinivasan, A. Bailey, Lam Research Corporation, “Raising the bar on wafer edge yield – an etch perspective”, Solid State Technology, November, 2008.
[14] Anngret Wieters, Peter Thieme, “Wafer edge / bevel treatment of device wafers by means of CMP”, International Conference on Planarization/CMP Technology, Session 7, pp. 173-176, October 25-27, 2007.
[15] Fang, Tong, Bailey III, Andrew D.,Kim, Yunsang, Rigoutat, Olivier, Stojakovic, George., “Copper Discoloration Prevention Following Bevel Etch Process”, US Patent, July 2, 2009.
[16] Eiji Kakiuchi, “Development of new wafer edge etching and cleaning technology- Improved processing precision contributes to increases in semiconductor device production efficiency and yields”, News Release Doc. No.: NR081024E, October 24, 2008
[17] Chapman Technical “Semiconductor wafer edge analysis”, Chapman Technical Note-TW-1 waf_edge.doc, Rev-98-07.
[18] John A. Allgair; Christopher J. Raymond, “Automated defect review of the wafer bevel with a defect review scanning electron microscope”, Metrology, Inspection, and Process Control for Microlithography XXIII, Proc. SPIE, Vol. 7272, March-23, 2009.
[19 ]Hideo Ota, Masayuki Hachiya, Yoji lchiyash, Toru Kurenuma, ”Scanning surface inspection
system with defect-review SEM and analysis system solutions”, Hitachi Review, Vol. 55, No. 2, pp. 78-85, June, 2006.
[20] Kalyan Jami, Srini Vedula, Gerry Blumenstock, KLA-Tencor Corporation, Kim, Yunsang Kim, Yung Kim, Lam Research Corporation, “Optimization of edge die yield through defectivity reduction”, Solid State Technology, October, 2009.
[21] Jeong Yeal Kim, “Wafer edge exposure apparatus, and wafer edge exposure method”, Yokohama, Japan, US Patent 6875971. April 5, 2005.
[22] Kia Huat Gan, Yew-Kong Tan and Gin P. Sun, “Wafer edge dies yield Improvements", Proc. SPIE, Vol. 4344, p. 274, 2001.
[23] K. Jami, I. Pollentier, S. Vedula and G. Blumenstock, “Influence of immersion lithography on wafer edge defectivity”, p. 656, February, 2010 (ISBN 978-953-307-064-3).
[24] Chen-Fu Chien, Shao-Chung Hsu, and Chih-Ping Chen, “An iterative cutting procedure for determining the optimal wafer exposure pattern”, Vol. 12, Issue 3, pp. 375-377, August, 1999.
[25] Nobuyoshi Sato, Chris Bowker, Leo Archer, “Using a single-wafer spin system to prevent dielectric film peeling”, Solid State Technology, June, 2005.
[26] J. D. Morillo, T. Houghton, J.M. Bauer, R. Smith, R. Shay, “Edge and bevel automated defect inspection for 300 mm production wafer in manufacturing”, Advanced Semiconductor Manufacturing Conference and Workshop, 2005 IEEE/SEMI, pp. 49-52, June, 2005 (ISBN 0-7803-8997-2).
[27] Christine Bunke; Thomas F. Houghton; Kenneth Bandy; George Stojakovic; Grace Fang, “Bevel RIE Application to Reduce Defectivity in Copper BEOL Processing”, Transactions on Semiconductor Manufacturing, 2013 IEEE, pp. 442-447.
[28] Andrew Stamper; Sang Chong; Kourosh Nafisi; Petra Feichtinger; WeeTeck Chia; David Randall; Aneesh Khullar, “Novel, Sem-Based Method for Wafer Inspection Recipe Optimization”, Advanced Semiconductor Manufacturing Conference, 2007 IEEE/SEMI, pp. 195-200.
[29] Harriman Razman; Mohd Faizal Adris; Cha Tree Tow Woon, “Implementing air ionizing blower at KLA Tencor 2401 metrology tool reduce visual inspection failure for semiconductor wafers”, Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD) , 9-14 Sept. 2012, pp. 1-6.
[30] Xiaofeng Yuan; Qiang Zhang; Jing'an Hao, “Wafer edge treatment in lithographic process for peeling defect reduction”, Semiconductor Technology International Conference (CSTIC), 2017 China, pp. 1-4.