簡易檢索 / 詳目顯示

研究生: 王鴻鈞
Wang, Hung-Chun
論文名稱: 不同製程及元件設計之高電壓雙擴散金氧半場效電晶體其特性及熱載子退化行為
Characteristics and Hot-Carrier Behavior of High Voltage Double-Diffused-Drain (DDD) MOSFET with Different Process and Device Design
指導教授: 陳志方
Chen, Jone Fang
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年: 2005
畢業學年度: 93
語文別: 英文
論文頁數: 81
中文關鍵詞: 雙擴散電晶體熱載子可靠度高壓元件
外文關鍵詞: hot-carrier reliability, HV-MOSFET, DDD-MOSFET
相關次數: 點閱:55下載:5
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  •   本篇論文主要是在探討高電壓雙擴散(DDD)金氧半場效電晶體之特性與熱載子退化行為。由於雙擴散金氧半場效電晶體為輕摻雜汲極(LDD)場效電晶體之過渡結構,故相關研究實屬不多。我們發現其DDD結構可提升元件崩潰電壓,可以作為高壓元件操作。我的研究主要是探討此高壓元件在改變不同製程參數下元件的直流特性及熱載子可靠度的關係,並進一步探討元件之退化行為。對雙擴散結構而言,其輕摻雜區域(NDD)也是我們探討的重點之一。我們認為雖然輕摻雜區域有助於提升崩潰電壓,但同時也會降低元件效能及改變熱載子退化行為。
      在我的研究中所改變的製程條件有3種,分別為1) NDD濃度; 2) P-field與Deep implant; 3)LDD結構,首先我們用HP-4155量測並探討在各種不同製程條件下之直流特性。接著分別對元件作熱載子可靠度測試,討論各個參數在不同製程條件及不同電壓下的退化程度。同時,我們也比較不同的結構下的特性,分別有 1) 厚氧化層vs.薄氧化層,2)改變閘極到汲極寬度。藉由一連串的比較,便可以了解不同製程條件與結構對元件特性及熱載子可靠度之影響。

     In this paper, the discussion is focused on the characteristics and hot-carrier behavior of HV Double-Diffused-Drain (DDD) MOSFETs. As DDD MOSFETs is the transitional structure of LDD MOSFETs, related documents about hot-carrier reliability are limited. Because DDD structure can increase breakdown voltage, DDD MOSFETs can be used as HV MOSFETs. My research is aimed at investigating the performance with different process flow and structure, the relation on hot-carrier reliability, and to discuss the degradation behavior of devices.
     There are three different process conditions discussed in my paper, they are 1) NDD dose; 2) p-field, and deep implant 3) LDD structure, respectively. First, we measure device performance of different process condition using HP-4155, the semiconductor parameter analyzer instrument. Then the devices are stressed to evaluate the degradation magnitude of different stress voltage and process condition. Meanwhile, we also investigate the difference under different device structure, they are 1) thick-oxide vs. thin-oxide; 2) gate-to-drain space, respectively. With a series of comparison, we can understand the effect of each process condition and structure on device performance and hot-carrier reliability.

    Abstract (Chinese) …………………………………………………Ⅰ Abstract (English) …………………………………………………Ⅲ Contents ………………………………………………………………Ⅵ Figure Captions ………………………………………………………Ⅸ List of Tables ………………………………………………………XⅢ Chapter 1 Introduction ………………………………………………1 1.1 Introduction of HV application ………………………………1 1.2 About this paper …………………………………………………2 Chapter 2 Measurement & Stress of HV-MOSFET ……………………4 2.1 Introduction …………………………………………………4 2.2 Device Structure ……………………………………………4 2.2.1 Device Description ……………………………………4 2.2.2 Operating Principle of DDD-MOSFET ………………6 2.3 Measurement Methodology ……………………………………6 2.3.1 Measurement Setup ……………………………………7 2.3.2 ID-VD Measurement ……………………………………7 2.3.3 ID-VG Measurement ……………………………………7 2.3.4 ISUB-VG Measurement …………………………………8 2.3.5 Breakdown Voltage Measurement ……………………9 2.3.6 VT Extraction …………………………………………10 2.3.7 Subthreshold swing …………………………………10 2.4 Stress Methodology …………………………………………10 Chapter 3 Device Design and Process Split ………………………22 3.1 Introduction …………………………………………………22 3.2 Gate-To-Drain Space …………………………………………22 3.3 The Process Split ……………………………………………22 3.3.1 NDD dose …………………………………………………23 3.3.2 LDD implant ………………………………………………………24 3.3.3 P-field, deep implant …………………………………………25 3.4 The Gate Oxide Thickness …………………………………26 3.5 Summary …………………………………………………………27 Chapter 4 Characteristics and Hot-Carrier Behavior of the DDD Structure     ……………………………………………………………………31 4.1 Introduction ………………………………………………………31 4.2 Effect of Spacing S ………………………………………………31 4.3 Effect of process split on device characteristic …………33 4.3.1 NDD dose ……………………………………………………………34 4.3.2 LDD structure ……………………………………………………36 4.3.3 P-field, deep implant ……………………………………………37 4.4 Summary …………………………………………………………38 Chapter 5 Hot-Carrier Degradation in Double-Diffused Drain MOSFETs with         Different Gate Oxide Thickness …………………………55 5.1 Introduction ……………………………………………………55 5.2 Thick Oxide vs. Thin Oxide …………………………………55 5.2.1 Device characteristics ……………………………………………55 5.2.1 Hot-carrier reliability …………………………………………56 5.3 Summary ……………………………………………………………56 Chapter 6 Conclusion ………………………………………………………62 Reference ……………………………………………………………………63

    [1] S. Manzini and C. Contiero “Hot-Electron-Induced Degradation in High-Voltage Submicron DMOS Transistors”, ISPSD, pp.65 - 68 (1996)
    [2] S. Mahapatra, C. D. Parikh; V. R. Rao, C. R. Viswanathan and J. Vasi, “Device Scaling Effects on Hot-Carrier Induced Interface and Oxide-Trapped Charge Distributions in MOSFET’s” IEEE Trans. on Electron Devices, pp.789-796 (2000)
    [3] Y. Tsunashima, T. Wada, K. Yamada, T. Moriya, M. Nakamura, R. Dang, K. Taniguchi, M. Kashiwagi and H. Tango, “Metal-coated Lightly-Doped Drain (MLD) MOSFETs for Submicron VLSI,” VLSI Technology Symposium, pp.114 (1985)
    [4] J. S. Yuan and Y. Gu, “Gate-oxide thickness effects on hot-carrier-induced degradation in n-MOSFETs” International Journal of Electronics, pp.1-9 (1998)
    [5] A. Hori, S. Kameyama, M. Segawa, H. Shimomura and H. Ogawa, “A Self-Aligned Pocket Implantation (SPI) Technology for 0.2 micron Dual-Gate CMOS,” Technical Digest. IEDM, pp.641 (1991)
    [6] T. Y. Chan, P. K. Ko and C. Hu, “A Simple Method to Characterize Substrate Current in MOSFETs,” IEEE Electron Device Letts., pp.505 (1984)
    [7] J. Sanchez, K. Hsueh and T. DeMassa, “Drain-Engineered Hot-Electron-Resistant Device Structures: A Review” IEEE Translations on electron devices, pp.1125-1132 (1989)
    [8] S. H. Chen, J. Gong, M. C. Wu, T. Y. Huang, J. F. Huang, R. H. Liou, S. L. Hsu, L. L. Lee and H. C. Lee, ”Time-Dependent Drain- and Source-Series Resistance of High-Voltage Lateral Diffused Metal–Oxide–Semiconductor Field-Effect Transistors during Hot-Carrier Stress” Jpn. J. Appl. Phys., pp.409–413 (2003)
    [9] L. Selmi, E. Sangiorgi and B. Riccò, “Parameter Extraction from I-V Characteristics of Single MOSFET’s” IEEE Transactions on Electron Devices, pp.1094 (1989)
    [10] T. Wang, T. E. Chang, C. M. Huang, J. Y. Yang, K. M. Chang and L. P. Chiang “Structural effect on band-trap-band tunneling induced drain leakage in n-MOSFET's” IEEE Electron Device Letters, pp.566 (1995)
    [11] T. I. Liou, C. S. Teng, and Richard B. Merrill, “Hot-Electron-Induced Degradation of Conventional, Minimum Overlap, LDD and DDD N-Channel MOSFETs” IEEE Circuits and Devices Magazine, pp.9-15 (1988)
    [12] H. S. Kim; S. D. Kim, M. K. Han, S. N. Yoon, W. O. Lee, and Y. I. Choi “A lightly doped shallow junction extension for the high breakdown voltage by double diffusion process using the taper SiO2 mask” Power Semiconductor Devices and ICs, ISPSD, pp.335-339 (1995).
    [13] J. F. Chen and C. P. Tsao, “A New Observation in Hot-Carrier Induced Drain Current Degradation in Deep-Sub-Micrometer nMOSFETs” Proc. 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits(IPFA), pp.31-34 (2002)
    [14] B. J. Baliga, “An overview of smart power technology,” IEEE Trans. on Electron Devices, pp.1568 (1991)
    [15] 國立成功大學論文 The Characteristics of n-Channel Lateral Diffused Metal-Oxide-Semiconductor (LDMOS) Field Effect Transistors with Different Gate Oxide Thickness by C.C. Chen
    [16] 國立成功大學論文 Hot Carrier Reliability of n-channel Lateral Diffused Metal Oxide Semiconductor Field Effect Transistor (LDMOS) by K.W. Lin
    [17] Stanley Wolf Ph.D., “Silicon Processing For the VLSI Era” Volume 3: The Submicron MOSFET
    [18] S. M. Sze, Physics of Semiconductor Devices, 2nd Ed. John Wiley & Sons, 2002.

    下載圖示 校內:2008-07-06公開
    校外:2010-07-06公開
    QR CODE