隨著數位資料大量透過網路傳輸與儲存，資料完整性與資訊安全已成為重要議題。密碼學雜湊函數可將任意長度的輸入訊息轉換為固定長度的雜湊值，並可用於檢查資料是否遭到竄改。
美國國家標準暨技術研究院於2015年發布了基於Keccak海綿結構的SHA-3標準，其中SHA-3標準包含了多種不同輸出長度的雜湊模式，各模式在位元率、容量與雜湊輸出長度等參數上有所差異，可根據不同的應用需求選擇所需的模式，然而在實際硬體應用中，系統可能需要同時支援多種SHA-3雜湊模式，若針對四種模式分別實作獨立的運算核心，將重複配置Keccak置換運算與狀態暫存器等硬體資源，導致整體硬體資源使用量增加，為了提升硬體資源的使用效率，本研究提出了基於共享Keccak核心的多模式SHA-3硬體架構，使單一架構即可支援四種SHA-3雜湊模式。
本研究以Verilog硬體描述語言進行設計與實作，並以NCVerilog進行模擬與驗證，系統透過模式選擇訊號(Mode Select)，依所選模式動態調整資料填充邊界、有效吸收範圍與雜湊輸出長度，使四種SHA-3固定輸出模式共用同一組Keccak-f[1600]置換核心與1600位元內部狀態，輸出介面則採用固定64位元分段選擇方式，以降低最大輸出資料匯流排寬度，功能驗證採用12組位元率區塊邊界測試，硬體輸出皆與Python標準函式庫之參考結果一致，於相同Vivado 2021.1與Artix-7 XC7A100T-CSG324-1條件下完成Post-Implementation Routed資源分析後，四種固定模式核心之獨立實作資源總和為35,503個LUT與10,235個FF，而本研究多模式共享核心使用11,447個LUT與2,800個FF，分別降低約67.8%與72.6%，顯示共享核心可有效減少多模式硬體中重複配置的運算資源。

This study proposes a Multi-Mode SHA-3 Hardware Architecture based on a Shared Keccak Core to reduce repeated hardware resources when several SHA-3 hash modes must be supported in one system. The design supports SHA3-224, SHA3-256, SHA3-384, and SHA3-512 through an external Mode Select signal. According to the selected mode, the hardware dynamically adjusts the Padding Boundary, Effective Absorption Range, and Hash Output Length, while all modes share one Keccak-f[1600] Permutation Core and one 1600-bit Internal State. The architecture is implemented in Verilog and verified using NCVerilog. A Fixed 64-bit Segment-Select Output Interface is also used to reduce the maximum output Data Bus Width. Functional verification includes 12 Rate Block Boundary Tests, and all hardware results match the reference values generated by the Python standard library. Under the same Vivado 2021.1 and Artix-7 XC7A100T-CSG324-1 implementation conditions, the Sum of the Four Fixed-Mode Cores requires 35,503 LUTs and 10,235 FFs, while the proposed Multi-Mode Shared Core uses 11,447 LUTs and 2,800 FFs. The corresponding Resource Reduction is approximately 67.8% for LUTs and 72.6% for FFs.

[1] National Institute of Standards and Technology, SHA-3 Standard: Permutation-Based Hash and Extendable-Output Functions, FIPS PUB 202, Aug. 2015.
[2] H. Hsing, “SHA3 Core Specification,” Rev. 0.1, OpenCores, Jan. 2013.
[3] A. E. Putra, O. Natan, and J. E. Istiyanto, “Optimizing FPGA resource allocation for SHA-3 using DSP48 and pipelining techniques,” IIUM Engineering Journal, vol. 26, no. 1, pp. 240–253, 2025.
[4] G. Bertoni, J. Daemen, M. Peeters, and G. Van Assche, “Keccak sponge function family main document,” Version 2.1, Jun. 2010.
[5] G. Bertoni, J. Daemen, M. Peeters, and G. Van Assche, “The Keccak Reference,” Version 3.0, Jan. 2011.
[6] K. Latif, M. M. Rao, A. Aziz, and A. Mahboob, “Efficient hardware implementations and hardware performance evaluation of SHA-3 finalists,” in Proc. 3rd SHA-3 Candidate Conf., Washington, DC, USA, Mar. 2012.
[7] B. Baldwin, A. Byrne, L. Lu, M. Hamilton, N. Hanley, M. O’Neill, and W. P. Marnane, “FPGA implementations of the round two SHA-3 candidates,” in Proc. Int. Conf. Field Programmable Logic and Applications (FPL), 2010, pp. 400–407.
[8] J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, 6th ed. Morgan Kaufmann, 2017.
[9] K. Gaj, E. Homsirikamol, and M. Rogawski, “Fair and comprehensive methodology for comparing hardware performance of fourteen round two SHA-3 candidates using FPGAs,” in Cryptographic Hardware and Embedded Systems—CHES 2010, pp. 264–278, 2010.
[10] A. Sideris and M. Dasygenis, “Enhancing the hardware pipelining optimization technique of the SHA-3 via FPGA,” Computation, vol. 11, no. 8, Art. no. 152, 2023.
[11] B. Baldwin, A. Byrne, L. Lu, M. Hamilton, N. Hanley, M. O’Neill, and W. P. Marnane, “A hardware wrapper for the SHA-3 hash algorithms,” in Proc. IET Irish Signals and Systems Conf., Maynooth, Ireland, 2010, pp. 1–6.