摘要
　　被動濾波器一直廣泛地被應用在電子電路與系統，傳統的設計方法是利用數學式去趨近濾波器的理想特性曲線，設計者藉著數學運算來完成濾波器的合成，然而，這種方法有其限制所在，因為它將元件的值視為是理想的、連續的而且沒有考慮到寄生效應。由於對自然界演化機制的理解與現代電腦能力的進步而產生的演化計算的方法論提供了研究者另一路數，演化計算的方法將電路合成視為是一種搜尋問題，因而有能力找出不同且優於傳統的電路。
　　本論文提出一種樹狀結構及一個基因規劃法用來做被動濾波器的合成。首先，我們做一些實驗來看適應度函數與控制參數對此基因規劃法的效能之影響，這些結果將作為爾後調整效能之依據；之後，我們將之併入一個迭代的演算法中，此一演算法可以用來合成較經濟的電路；接著，這個方法被用於不同的濾波器的設計例子，這些例子包含如下的實際設計考量，即：元件的值為離散、有誤差值，寄生效應以及群延遲；此外，我們將這個方法稍加修改，並應用到阻抗匹配的問題上。實驗結果顯示，利用基因規劃法能有效地產生符合實際考量而又經濟的設計。

Abstract
　Passive filters have been widely used in electronic circuits and systems, since they were first developed in the early twentieth century. The traditional passive filter synthesis methods are to find a mathematic formula which can approximate the ideal brick-like transfer function representing the behavior of filters. After that, the filter designers can perform filter synthesis by manipulating that mathematical formula. However, this kind of mathematic approaches is limited in practice because the components are assumed to be having a continuous and nominal value, and free from parasitic effects. Evolutionary approaches, inspired by the understanding of the mechanism of natural evolution and the increase of modern computers’ capability, provide the researchers with alternative methodology. The evolutionary approaches, viewing filter synthesis as a search problem, are capable of finding novel circuits superior to the traditional ones.
　In the thesis, a novel tree representation of RLC circuits and a genetic programming (GP) method based on the representation are proposed to deal with the problems of passive filter synthesis. Experiments are performed to investigate how fitness function and control parameters affect the performance of the GP, which is then well tuned and incorporated into an iterative algorithm which can generate economical solutions. This algorithm is applied to a number of filter design cases where the following practical design considerations are taken into account: discrete component values, component tolerance, parasitic effects, and group delay. In addition, the GP method is modified and applied to impedance matching problems. The experimental results show the proposed method can effectively generate not only practical but also economical solutions in all cases.

[1] J. H. Holland, Adaptation in Natural and Artificial Systems. Ann Arbor, MI: Univ. Michigan Press, 1975.
[2] D. E. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning. Reading MA: Addison-Wesley, 1989.
[3] M. Zbigniew, Genetic Algorithms + Data Structures = Evolution Programs. 3rd ed., Berlin: Springer-Verlag, 1996.
[4] G. Alpaydin, S. Balkir, and G. Dundar, “An evolutionary approach to automatic synthesis of high-performance analog integrated circuits,” IEEE Trans. Evol. Comput., vol. 7, no. 3, pp. 240–252, June 2003.
[5] D. Andre, F. H Bennett III, J. R. Koza, F.H., and M. A. Keane, “On the theory of designing circuits using genetic programming and a minimum of domain knowledge,” in Proc. 1998 IEEE Int. Conf. Evolutionary Computation, 1998, pp. 130–135.
[6] G. Ascia, V. Catania, and M. Palesi, “A GA-based design space exploration framework for parameterized system-on-a-chip platforms,” IEEE Trans. Evol. Comput., vol. 8, no. 4, pp. 329–346, Aug. 2004.
[7] T. R. Dastidar, P. P. Chakrabarti, and P. Ray, “A synthesis system for analog circuits based on evolutionary search and topological reuse,” IEEE Trans. Evol. Comput., vol. 9, no. 2, pp. 211–224, Apr. 2005.
[8] H. DeGaris, Evolvable Hardware: Genetic Programming of a Darwin Machine, in Artificial Neural Nets and Genetic Algorithms. R. F. Albretch, C. R. Reeves, N. C. Steele, Eds., New York: Springer-Verlag, 1993.
[9] J. B. Grimbleby, “Automatic analogue network synthesis using genetic algorithms,” in Proc. First Int. Conf. Genetic Algorithms in Engineering Systems: Innovations and Applications (GALESIA). London: Institution of Electrical Engineers, 1995, pp. 53–58.
[10] J. B. Grimbleby, “Automatic analogue circuit synthesis using genetic algorithms,” IEE Proc.-Circuits Devices Syst., vol. 147, no. 6, pp. 319–323, Dec. 2000.
[11] D. H. Horrocks and Y. M. A. Khalifa, “Genetically derived filter circuits using preferred value components,” in Proc. IEE Colloq. on Linear Analogue Circuits and Systems, Oxford, UK, 1994, pp. 4/1–4/5
[12] —, “Genetic algorithm design of electronic analogue circuits including parasitic effects,” in Proc. First On-line Workshop on Soft Computing (WSC1), Nagoya Univ., Japan, Aug. 1996.
[13] J. R. Koza, F. H Bennett III, D. Andre, and M. A. Keane, “Automated WYWIWYG design of both the topology and component values of analog electrical circuits using genetic programming,” in Genetic Programming 1996: Proc. First Annu. Conf., J. R. Koza, D. E. Goldberg, D. B. Fogel, and R. L. Riolo, Eds. Cambridge, MA: MIT Press, 1996, pp. 123–131.
[14] —, “Reuse, parameterized reuse, and hierarchical reuse of substructures in evolving electrical circuits using genetic programming,” in Proc. Int. Conf. Evolvable System: From Biology to Hardware (ICES-96) (Lecture Notes in Computer Science), vol. 1259, Berlin: Springer-Verlag. 1996, pp. 312–326.
[15] —, “Use of automatically defined functions and architecture-altering in Genetic Programming,” in Genetic Programming 1996: Proc. First Annu. Conf., J. R. Koza, D. E. Goldberg, D. B. Fogel, and R. L. Riolo, Eds., Cambridge, MA: MIT Press, 1996, pp. 132–140.
[16] —, “Evolution of a 60 decibel op amp using genetic programming,” in Proc. Int. Conf. Evolvable System: From Biology to Hardware (ICES-96) (Lecture Notes in Computer Science), T. Higuchi, Ed., vol. 1259, Berlin: Springer-Verlag. 1996, pp. 455–469.
[17] J. R. Koza, F. H Bennett III, D. Andre, M. A. Keane, and F. Dunlap, “Automated synthesis of analog electrical circuits by means of genetic programming,” IEEE Trans. Evol. Comput., vol. 1, no. 2, pp. 109–128, July 1997.
[18] J. R. Koza, F. H Bennett III, J. Lohn, F. Dunlap, D. Andre, and M. A. Keane, “Use of architecture-altering operations to dynamically adapt a three-way analog source identification circuit to accommodate a new source,” in Genetic Programming 1997: Proc. Second Annu. Conf., J. R. Koza, D. Kalyanmoy, M. Dorigo, D. B. Fogel, M. Garzon, H. Iba, Hitoshi, and R. L. Riolo, Eds., San Francisco, CA: Morgan Kaufmann, 1997, pp. 213–221.
[19] —, “Automated synthesis of computational circuits using genetic programming,” in Proc. 1997 IEEE Conf. Evolutionary Computation. Piscataway, NJ, IEEE Press pp. 447–452, 1997.
[20] J. R. Koza, F. H Bennett III, M. A. Keane, and D. Andre, “Evolution of a time-optimal fly-to controller circuit using genetic programming,” in Genetic Programming 1997: Proc. Second Annu. Conf., J. R. Koza, D. Kalyanmoy, M. Dorigo, D. B. Fogel, M. Garzon, H. Iba, Hitoshi, and R. L. Riolo, Eds., San Francisco, CA: Morgan Kaufmann, 1997, pp. 207–212.
[21] J. R. Koza, F. H Bennett III, D. Andre, and M. A. Keane, Genetic Programming III: Darwinian Invention and Problem Solving. San Francisco, CA: Morgan Kaufmann, 1999.
[22] M. W. Kruiskamp and D. Leenaerts, “DARWIN: CMOS opamp synthesis by means of a genetic algorithm,” in Proc. 32nd Design Automation Conf., NewYork: Assoc. Comput. Mach., 1995, pp. 433–438.
[23] M. W. Kruiskamp, Analog Design Automation Using Genetic Algorithms and Polytopes. Eindhoven, The Netherlands: Data Library Technische Universiteit Eindhoven, 1996.
[24] W. Liu, M. Murakawa, and T. Higuchi, “ATM cell schedule by function level evolable hardware,” in Proc. First Int. Conf. Evolvable System: From Biology to Hardware (ICES-96), Tsukuba, Japan, G. Goos, J. Hartmanis, and J. van Leeuwen, Eds., vol. 1259, LNCS, Berlin: Springer-Verlag, 1996, p. 180.
[25] J. D. Lohn, and S. P. Colombano, “A circuit representation technique for automated circuit design,” IEEE Trans. Evol. Comput., vol. 3, no. 3, pp. 205–219, Sept. 1999.
[26] J. D. Lohn and G. L. Haith, “A comparison of dynamic fitness schedules for evolutionary design of amplifiers,” in Proc. of the First NASA/DoD Workshop on Evolvable Hardware, A. Stoica, D. Keymeulen, and J. Lohn, Eds., Pasadena, CA, July 1999, pp. 87–92.
[27] S. J. Louis and J. E. Rawlins, “Designer genetic algorithms: genetic algorithms in structure design,” in Proc. of the Fourth Int. Conf. on Genetic Algorithms (ICGA-91), R. K. Belew, L. B. Booker, and M. Kauffman, Eds., 1991, p. 53.
[28] J. F. Miller, P. Thomson, and T. Fogarty, “Designing electronic circuits using evolutionary algorithms, arithmetic circuits: a case study,” in Genetic Algorithms Recent Advancements and Industrial Applications, D. Quagliarella, J. Periaux, C. Poloni, and G. Winter, Eds., New York: Wiley & Sons, 1997, chap. 6.
[29] E. Sanchez, D. Mange, M. Sipper, T. Tomassini, A. Perez-Uribe, and A. Stauffer, “Phylogeny, ontogeny and epigenesist: three sources of biological inspiration for softening hardware,” in Proc. First Int. Conf. Evolvable System: From Biology to Hardware (ICES-96), Tsukuba, Japan, G. Goos, J. Hartmanis, and J. van Leeuwen, Eds., vol. 1259, LNCS, Berlin: Springer-Verlag, 1996, p. 35.
[30] T. Schnier, X. Yao, and P. Liu, “Digital filter design using multiple pareto fronts,” Soft Computing, vol. 8, no. 5, pp. 332–343, Apr. 2004.
[31] H. Shibata and N. Fujii, “An evolutionary synthesis of analog active circuits using current path based coding,” IEICE Trans. Fundamentals, vol. E84-A, no. 10, pp. 2561–2568, Oct. 2001.
[32] H. Shibata and N. Fujii, “Analog circuit synthesis based on reuse of topological features of prototype circuits,” IEICE Trans. Fundamentals, vol. E84-A, no. 11, pp. 2778–2784, Nov. 2001.
[33] A. Thompson, “Silicon evolution,” in Proc. of Genetic Programming 1996 (GP96), J. R. Koza et al. Eds., Cambridge: MIT Press, 1994, p. 444.
[34] A. Thompson, “On the automatic design of robust electronics through artificial evolution,” in Proc. Second Int. Conf. Evolvable System: From Biology to Hardware (ICES-98), Lausanne, Switzerland, M. Sipper, D. Mange, and A. Perez-Ubribe, Eds., vol. 1478, LNCS, Springer-Verlag, 1998, p. 13.
[35] P. L. Werner, R. Mittra, and D. H. Werner, “Extraction of SPICE-type equivalent circuits of microwave components and discontinuities using the genetic algorithm optimization technique,” IEEE Trans. Advanced Packaging, vol. 23, no. 1, pp. 55–61, Feb. 2000.
[36] R. S. Zebulum, M. A. Pacheco, and M. Vellasco, “Comparison of different evolutionary methodologies applied to electronic filter design,” in Proc. 1998 IEEE Int. Conf. Evolutionary Computation, 1998, pp. 434–439.
[37] R. S. Zebulum, M. A. Pacheco, and M. M. Vellasco, “Artificial evolution of active filters: a case study,” in Proc. of the First NASA/DoD Workshop on Evolvable Hardware, A. Stoica, D. Keymeulen, and J. Lohn, Eds., Pasadena, CA, July 1999, pp. 66–75.
[38] P. Mazumder and E. M. Rudnick, Genetic Algorithms for VLSI Design, Layout, and Test Automation. Prentice Hall, 1999.
[39] R. S. Zebulum, M. A. Pacheco, and M. M. Vellasco, Evolutionary Electronics: Automatic Design of Electronic Circuits and Systems by Genetic Algorithms. New York: CRC Press, 2002.
[40] J. R. Koza, Genetic Programming: On the Programming of Computers by Means of Natural Selection. Cambridge, MA: MIT Press, 1992.
[41] B. I. P. Rubinstein, “Evolving quantum circuits using genetic programming,” in Proc. 2001 Congress on Evolutionary Computation (CEC2001), vol.1, May 2001, pp. 144–151.
[42] M. Lukac and M. Perkowski, “Evolving quantum circuits using genetic algorithm,” in Proc. 2002 NASA/DoD Conf. on Evolvable Hardware (EH’02) IEEE Int. Conf. Evolutionary Computation, July 2002, pp. 177–185.
[43] M. H. A. Khan and M. Perkowski, “Genetic algorithm based synthesis of multi-output ternary functions using quantum cascade of generalized ternary gates,” in Proc. 2004 Congress on Evolutionary Computation (CEC2004), vol.2, June 2004, pp. 2194–2201.
[44] I. Bahl, Lumped Elements for RF and Microwave Circuits. Norwood, MA: Artech House, 2003.
[45] K. Su, Analog Filters. Norwell, MA: Kluwer Academic Publishers, 2nd edn., 2002.
[46] H. J. Blinchikoff and A. I. Zverev, Filtering in the Time and Frequency Domains. New York: John Wiley & Sons, 1976.
[47] J. P Caisso, E. Cerny, and N. C. Rumin, “A recursive technique for computing delays in series-parallel MOS transistor circuits,” IEEE Trans. Computer-Aided Design, vol. 10, no. 5, pp. 589–595, May 1991.
[48] M. Chang and W. S. Feng, “A recursive algorithm for estimating the internal charge sharing effect in RC tree circuits,” IEICE Trans. Fundamentals, vol. E81-A, no. 5, pp. 913–923, May 1998.
[49] M. Chang, W. J. Chen, J. H. Wang, and W. S. Feng, “An algorithm for estimating bottleneck effect in series-parallel tree circuits,” IEICE Trans. Fundamentals, vol. E81-A, no. 11, pp. 2400–2406, Nov. 1998.
[50] J. H. Wang, M. Chang, and W. S. Feng, “Binary-tree timing simulation with consideration of internal charges,” IEE Proceedings-E, vol. 140, no. 4, pp. 211–219, July 1993.
[51] T. M. Lin and C. A. Mead, “Signal delay in general RC networks,” IEEE Trans. Computer-Aided Design, vol. CAD-3, no. 4, pp. 331–349, Oct. 1984.
[52] M. Main, Data Structures and Other Objects Using Java. Reading, MA: Addison-Wesley, 1999, pp. 446–450.
[53] W. Banzhaf, P. Nordin, R. E. Keller, and F. D. Francone, Genetic Programming—An Introduction: On the Automatic Evolution of Computer Programs and Its Applications. San Francisco, CA: Morgan Kaufmann, 1998, pp. 134–135.
[54] P. M. Lin, “Single curve for determining the order of an elliptic filter,” IEEE Trans. Circuits Syst., vol. 37, no. 9, pp. 1181–1183, Sept. 1990.
[55] A. I. Zverev, Handbook of Filter Synthesis. New York: John Wiley & Sons, 1967, p. 142.
[56] R. Spence and R.S. Soin, Tolerance Design of Electronic Circuits. New York: Addison-Wesley, 1988.
[57] M. D. Meehan and J. Purviance, Yield and Reliability in Microwave Circuit and System Design. Norwood, MA: Artech House, 1993, pp.211–218.
[58] M. A. Owadally and J. Greene, “Evolutionary optimization in the search for intrinsically robust circuit designs,” in Proc. IEEE Int. Symp. on Industrial Electronics (ISIE '98), vol.1, pp.182–185, July 1998.
[59] C. A. Corral, “Nomographs and classical filter sensitivity optimization,” in Proc. IEEE Int. Symp. on Circuits and Syst. (ISCAS 2002), vol.1, pp.I-541–I-544, May 2002.
[60] K. Hajek and J. Sedlacek, “General multiple LC prototype filter solutions and optimization,” in Proc. IEEE 9th Int. Conf. on Electron., Circuits and Syst., vol.1, pp.165–168, Sept. 2002.
[61] R. Menozzi, A. Piazzi, amd F. Contono, “Small-signal modeling for Microwave FET linear circuits based on a genetic algorithm,” IEEE Trans. Circuit Syst. I, vol. 43, no. 10, pp. 839–847, Oct. 1997
[62] P. L. Werner, R. Mittra, and D. H. Werner, “Extraction of SPICE-type equivalent circuits of microwave components and discontinuities using the genetic algorithm optimization technique,” IEEE Trans. Advanced Packaging, vol. 23, no. 1, pp. 55–61, Feb. 2000.
[63] Editor-in-chief, W. K. Chen, The Circuits and Filters Handbook. CRC Press in cooperation with IEEE Press, 1995, Chapter 21.
[64] J. W. Nilsson and S. A. Riedel, Electronic Circuits. Reading, MA: Addison-Wesley, 1996, 5th end., pp. 590–593.
[65] R. Sedgewick, Algorithms in C: Parts 1-4, Fundamentals, Data Structures, Sorting, Searching. Reading, MA.: Addison-Wesley, 1998, 3rd edn., pp. 179–183.
[66] H. J. Carlin and P. Amstutz, “On optimum broad-band matching,” IEEE Trans. Circuits Sys., vol. CAS-28, pp. 401–405, 1981.
[67] H. J. Carlin and B.S. Yarman, “The double matching problem: Analytic and real frequency solutions,” IEEE Trans. Circuits Sys., vol. CAS-30, pp. 15–28, 1983.
[68] H. Dedieu, C. Dehollain, J. Neirynck, and G. Rhodes, “A new method for solving broadband matching problems,” IEEE Trans. Circuits Sys.-I: Fund. Theory Appl., vol. 41, pp. 561–571, 1994.
[69] Y. Sun and W. K. Lau, “Antenna impedance matching using genetic algorithms,” in Proc. National Conf. on Antennas and Propagation, 1999, pp. 31–36.
[70] W. P. du Plessis and P. L. D. Abrie, “Lumped impedance matching using a hybrid genetic algorithm,” Microwave Opt. Technol. Lett., vol. 37, pp. 210–212, 2003.
[71] J.R. Long, “Passive components for silicon RF and MMIC design,” IEICE Trans. Electron., vol.E86-C, no.6, pp.1022–1031, June 2003.