三維晶片( 3D IC )技術以矽穿孔( Through-Silicon Via, TSV )做為核心建構的垂直式晶片封裝技術，能將功能各異的晶片以堆疊的方式連接，達成高線路密度與多功能的需求。TSV結構做為導線容易在通電時產生熱，使各層材料因為熱膨脹係數不同而產生熱應力，促使整個結構的失效並產生缺陷，而雙層堆疊的晶圓在介面的應力影響更為劇烈，本文想要透過製作不同環境下接合的雙層堆疊試片後，利用時間相依介電層熱破壞實驗( Time Dependent Dielectric Break down,TDDB )的電流-時間曲線來了解製程條件對試片的影響，再藉由模擬與實驗驗證後，以期能推廣至不同溫度與電壓條件得到試片的可行工作區域。
實驗上首先以生物晶片( Bio Chip )為發想，透過KOH濕蝕刻將晶圓薄化至120μm左右後，以高分子凝膠BCB ( Benzocyclobutene )將兩片晶圓進行堆疊，使用快速退火爐( Rapid Thermal Annealing Furnace , RTA )製作四種不同環境下接合試片，分別為一般大氣下、通入氮氣(N2)、真空度( 2×10-2 torr )’、高真空度( 5×10-5 torr )，以感應式耦合電漿離子蝕刻系統( Inductive Coupled Plasma Etching System )製作出直徑25μm、深160μm的高深寬比圓形導孔，填入700nm的鈦金屬阻障層( Barrier layer )與200nm的二氧化矽介電層( Dieletric layer )，最終利用電鍍方式的孔洞填銅來完成導線製作。熱破壞實驗則是利用一加熱載盤對試片加熱並施加定電壓進行100秒，直到到達崩潰電流為止，從中取得電流-時間曲線後搭配模擬來得知各層破壞時間與測試電壓值。
觀察熱破壞所取得的電流-時間曲線，可知高真空度下環境接合的試片擁有高耐壓且工作時間較長，證明腔體環境對介面的影響。電流變化模擬與實驗之結果比對後，發現數值相互吻合，由此可證實數值分析模型的正確性，因此模型建立後，可以調變不同的製程溫度與測試電壓，得到相對應的電流-時間曲線，此曲線之下面積代表不會產生電流崩潰即為各試件工作區域。

Three-dimensional chip (3D IC) technology came into being. Mainly Using Through-Silicon Via to build the vertical wafer packaging technology allowed to connect different functional wafers in a stacked manner to achieve high line density and versatility. As a connecting wire, TSV was easy to generate heat when electricity passed through and affected differently to the thermal expansion of every layer with different materials. TSV could result in the instability of the entire structure and even cause defects, which was the problem remaining to be resolved.
This study focused on the experimental and numerical results proved by the thermally-induced failures in the components of copper through-silicon via structures. All chips adopted via after bonding method and were stacked with the polymer gel BCB (Benzocyclobutene).This paper used Rapid Thermal Annealing Furnace (RTA) to joint test sample under four different environments, including normal atmosphere, N2, vacuum (2×10-2torr), and high vacuum (5×10-5torr).The thermal destroying experiments were carried out by time-Dependent Dielectric Layer Breakdown (TDDB) with joint test pieces under different environments. Plus, the failure time of each layer was verified by ANSYS / LS-DYNA numerical simulation.

[1]D. Diehl, H. Kitada, N. Maeda, K. Fujimoto, S. Ramaswami, K. Sirajuddin, R. Yalamanchili, B. Eaton, N. Rajagopalan, and R. Ding, “Formation of TSV for the stacking of advanced logic devices utilizing bumpless wafer-on-wafer technology,” Microelectronic Engineering, vol. 92, pp. 3-8, 2012.
[2]Z. Ren, and M. E. McNie, “Inductively coupled plasma etching of tapered via in silicon for MEMS integration,” Microelectronic Engineering, vol. 141, pp. 261-266, 2015.
[3]X. Wang, W. Zeng, G. Lu, O. L. Russo, and E. Eisenbraun, “High aspect ratio Bosch etching of sub-0.25 μ m trenches for hyperintegration applications,” Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena, vol. 25, no. 4, pp. 1376-1381, 2007.
[4]J. Van Aelst, H. Struyf, W. Boullart, and S. Vanhaelemeersch, “High aspect ratio via etch development for Cu nails in 3-D-stacked ICs,” Thin Solid Films, vol. 516, no. 11, pp. 3502-3506, 2008.
[5]N. Ranganathan, L. Ebin, L. Linn, W. S. V. Lee, O. Navas, V. Kripesh, and N. Balasubramanian, "Integration of high aspect ratio tapered silicon via for through-silicon interconnection." pp. 859-865,2008.
[6]Y. Yang, R. Labie, F. Ling, C. Zhao, A. Radisic, J. Van Olmen, Y. Travaly, B. Verlinden, and I. De Wolf, “Processing assessment and adhesion evaluation of copper through-silicon vias (TSVs) for three-dimensional stacked-integrated circuit (3D-SIC) architectures,” Microelectronics Reliability, vol. 50, no. 9, pp. 1636-1640, 2010.
[7]C. Huang, Q. Chen, D. Wu, and Z. Wang, “High aspect ratio and low capacitance through-silicon-vias (TSVs) with polymer insulation layers,” Microelectronic Engineering, vol. 104, pp. 12-17, 2013.
[8]C.-T. Ko, and K.-N. Chen, “Wafer-level bonding/stacking technology for 3D integration,” Microelectronics reliability, vol. 50, no. 4, pp. 481-488, 2010.
[9]B. Noia, and K. Chakrabarty, "Pre-bond probing of TSVs in 3D stacked ICs." pp. 1-10,2011.
[10]J. Hermanowski, "Thin wafer handling—Study of temporary wafer bonding materials and processes." pp. 1-5.
[11]K. Ko, M.-G. Song, H. Jeon, J. Han, B. U. Yoon, Y. Koh, C. Ahn, and T. Kim, “Characterization and removal of polysilicon residue during wet etching,” Microelectronic Engineering, vol. 149, pp. 85-91, 2016.
[12]G. Katti, A. Mercha, M. Stucchi, Z. Tokei, D. Velenis, J. Van Olmen, C. Huyghebaert, A. Jourdain, M. Rakowski, and I. Debusschere, "Temperature dependent electrical characteristics of through-si-via (TSV) interconnections." pp. 1-3.
[13]S.-H. Seo, J.-S. Hwang, J.-M. Yang, W.-J. Hwang, J.-Y. Song, and W.-J. Lee, “Failure mechanism of copper through-silicon vias under biased thermal stress,” Thin Solid Films, vol. 546, pp. 14-17, 2013.
[14]C.-C. Lee, and C.-C. Huang, “Induced thermo-mechanical reliability of copper-filled TSV interposer by transient selective annealing technology,” Microelectronics Reliability, vol. 55, no. 11, pp. 2213-2219, 2015.
[15]H.-J. Choi, S.-M. Choi, M.-S. Yeo, S.-D. Cho, D.-C. Baek, and J. Park, "An experimental study on the TSV reliability: Electromigration (EM) and time dependant dielectric breakdown (TDDB)." pp. 1-3.
[16]C.-F. Han, and J.-F. Lin, “Thermally-induced failures of copper through-silicon via structures evaluated by the strain energy density model,” Thin Solid Films, vol. 615, pp. 281-291, 2016.
[17]詹印丰, 颜锡鸿, and 许明哲, “TSV 制程技术整合分析 [J],” 半导体科技, vol. 5, 2010.
[18]A. Kafizas, C. J. Carmalt, and I. P. Parkin, “CVD and precursor chemistry of transition metal nitrides,” Coordination Chemistry Reviews, vol. 257, no. 13, pp. 2073-2119, 2013.
[19]張玉塵, 吳樸偉, “兩種含硫醇基添加劑對電鍍銅填孔力影響之研究,” 2008.
[20]北美智權報, “3D IC晶圓接合技術,no.半導體科技, 2014.
[21]蕭宏 ( Hong Xiao,半導體製程技術導論(第三版), 2015.
[22]李安平, 寇崇善, 吳敏文, 曾錦清, 蔡文發, 鄭國川, “電漿源原理與應用之介紹.”
[23]國科會南區微系統研究中心, “磁控濺鍍SOP( magnetron sputter ).”
[24]J. R. Black, “Electromigration—A brief survey and some recent results,” IEEE Transactions on Electron Devices, vol. 16, no. 4, pp. 338-347, 1969.
[25]郭亦哲, “矽穿孔結構之溫升效應下脫層及破壞之研究,” 成功大學機械工程學系學位論文, pp. 1-134, 2016.
[26]鄭義榮, 黃俊夫, 高楷傑, 黃麒嘉, “內連接導線系統之可靠度—銅導線/低介電絕緣層,” 國家奈米元件實驗室奈米通訊, vol. 20, no. 1, pp. 34-42, 2013.
[27]G. R. Johnson, and W. H. Cook, “Fracture characteristics of three metals subjected to various strains, strain rates, temperatures and pressures,” Engineering fracture mechanics, vol. 21, no. 1, pp. 31-48, 1985.
[28]劉建惟, “三維積體電路直通矽穿孔技術之應用趨勢與製程簡介,” Nano Communication, vol. 20, pp. 20-27, 2013.
[29]C.-F. Han, and J.-F. Lin, “The model developed for stress-induced structural phase transformations of micro-crystalline silicon films,” Nano-Micro Letters, vol. 2, no. 2, pp. 68-73, 2010.
[30]M. E. Mills, P. Townsend, D. Castillo, S. Martin, and A. Achen, “Benzocyclobutene (DVS-BCB) polymer as an interlayer dielectric (ILD) material,” Microelectronic Engineering, vol. 33, no. 1-4, pp. 327-334, 1997.