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研究生: 王昱舜
Wang, Yu-Shun
論文名稱: 鍺基板表面清洗、介面層與鐵電特性之研究
Investigation on Surface Cleaning, Interfacial Layer Formation, and Ferroelectric Properties on Germanium Substrates
指導教授: 高國興
Kao, Kuo-Hsing
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 奈米積體電路工程碩士博士學位學程
MS Degree/Ph.D. Program on Nano-Integrated-Circuit Engineering
論文出版年: 2018
畢業學年度: 106
語文別: 英文
論文頁數: 45
中文關鍵詞: 高介面品質負電容效應鉿鋯氧化物
外文關鍵詞: germanium, high interface quality, negative capacitance effect, Hf1-xZrxO
相關次數: 點閱:99下載:7
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  • 在本論文中,我們針對高性能與低功耗應用提出適用的方法。在高性能部分,我們提出具有高介面品質的鍺作為通道材料來增強驅動電流。隨著鰭狀通道高度越來越高,側壁上的傷害及缺陷影響變得更明顯,因此研究模仿蝕刻過的鰭狀通道側壁表面之影響,並且也討論表面處理條件、不同的閘極層與金屬後退火之影響。在低功耗部分,我們提出以鐵電材料作為閘極介電層,負電容效應已經被證實可以克服金氧半場效電晶體在室溫下次臨界擺幅60 mV/dec的限制,然而對於鍺金氧半電容器之鐵電特性相關研究仍十分缺乏,因此有系統地研究在鍺金氧半電容器與金屬-絕緣層-金屬結構上不同比例的鉿鋯氧化物之鐵電特性,此外也探討不同介面層與不同退火處理對鍺金氧半電容器之影響。

    In this thesis, we proposed some applicable approaches for both high performance and low power applications. For high performance applications, we have demonstrated germanium with high interface quality as channel materials to enhance the drive current. As the fin-height is higher, the effects of the damage and defects on the sidewall become more significant. The impacts of etched surface by mimicking the sidewalls of the etched fins are studied. The effects of surface treatment conditions, different gate stacks and post metal annealing are also discussed. For low power applications, ferroelectric materials as the gate dielectric are proposed. NC effects have been demonstrated to overcome the fundamental limit of subthreshold slope (SS) of 60 mV/dec at room temperature for MOSFETs. However, there is still lack of study on the ferroelectric properties of Ge metal-oxide-semiconductor capacitors (MOSCAPs). The ferroelectric characteristics of different Hf/Zr ratio of Hf1-xZrxO on Ge MOSCAPs and metal-insulator-metal (MIM) structures have been systematically studied. Besides, the impacts of different interfacial layers with different annealing treatment on Ge MOSCAPs have been also discussed.

    摘要 III Abstract IV 誌謝 V Contents VI Table Captions VII Figure Captions VIII Chapter I Introduction and Motivation 1 1-1 Scaling from Moore's Law 1 1-2 High Performance - Architectures and Materials Trend 2 1-3 Power-Constraint Scaling 3 1-4 Concept of Negative Capacitance 4 1-5 Motivation 6 1-6 Organization of the Thesis 6 Chapter II Ge Surface Cleaning and Interfacial Layer Formation 7 2-1 Experiment 7 2-2 Effects of Ge surface etching 8 2-3 Defects Passivation by FGA 12 2-4 Effects of NH3-plasma Treatment 15 2-5 Summary 17 Chapter III Ferroelectric Properties on Different Underlayers 18 3-1 Fabrication – MIM and Ge MOSCAPs 18 3-2 Ferroelectric Properties of 9 nm HZO (Hf/Zr = 1/1) 19 3-3 Ferroelectric Properties of 9 nm HZO (Hf/Zr = 1/3) 24 3-4 Effects for Long Time Annealing on Different Underlayers 30 3-5 Summary 39 Chapter IV Future Work 40 4-1 Switching Speed 40 4-2 FeRAM 40 References 42

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