由三五族半導體氮化鋁鎵/氮化鎵之異質結構所產生的極化特性，於兩者間導帶不連續處形成一量子井，使高濃度的電子被侷限於量子井內且少了雜質散射等影響，因此能在二維平面下進行高速移動，故稱其為二維電子氣(two dimensional electron gas, 2DEG)通道。此通道不僅擁有高電子遷移率，更因氮化鎵材料本身具有寬能隙、高崩潰電場、良好的熱穩定，使氮化鋁鎵/氮化鎵之異質結構半導體元件能在高溫、高頻下還能擁有良好的操作表現。本論文中引用氮化鋁鎵/氮化鎵異質結構所製作的空乏型(depletion mode)及增強型(enhancement mode)之金氧半高電子遷移率場效電晶體(MOS-HEMTs)結合，並將電路設計成共源極反相器電路，以形成空乏型元件與增強型元件串聯之互補式金氧半高電子遷移率場效電晶體元件(CMOS-HEMTs)，完成反相器作動之目的。
空乏型元件採用光電化學氧化法形成閘極氧化層，並使用光電化學蝕刻法進行不同蝕刻深度以調變空乏型元件操作電流。此法有別於傳統互補式電晶體利用閘極寬長比調變電流比例，容易因為兩者元件面積尺寸不一而增加整合於積體電路中的難易度，故透過蝕刻氮化鋁鎵薄膜厚度調變電流即可避免此問題，亦不影響該反相器作動的能力。
為了完成增強型元件操作之目的，使臨界電壓(threshold voltage, Vth)往正偏移，必須減少氮化鋁鎵薄膜厚度，降低二維電子氣通道內載子濃度，並同時提升閘極控制通道的能力。首先採用脈衝雷射沉積法(pulsed laser deposition technique)製作鈮酸鋰(lithium niobate, LiNbO3)鐵電薄膜作為堆疊式閘極氧化層最上層，利用其自發極化特性，並結合中間的電子捕捉層二氧化鉿(hafnium oxide, HfO2)薄膜捕捉電子與最下層的電子穿隧層三氧化二鋁(aluminum oxide, Al2O3)使電子穿隧並困於二氧化鉿中後不易跳回通道，達到更進一步空乏二維電子氣通道之目的，同時搭配光電化學(photoelectronchemical, PEC)濕式蝕刻法完成閘極掘入結構製作，使閘極更接近通道並提升閘極對通道的控制能力，完成增強型高速電子遷移率電晶體製作。
在負載端空乏型元件之氮化鋁鎵薄膜在經過蝕刻後所剩深度分別為12 nm、10 nm及8 nm下，空乏型元件與增強型元件的電流比例分別為5、8及22倍，並經過負載線特性分析、時域輸出波型及輸出輸入轉移曲線等反相器各項特性趨勢中，可以得知互補式場效電晶體元件在22倍的操作電流比例下將擁有較好的反相器輸出特性，操作在VDD為5 V、VIN為5 V的條件下，輸出擺幅(output swing)：4.90 V、雜訊邊際(noise margin)：NMH= 1.99 V、NML= 1.73 V，而當VOUT=2.5 V時，其VIN值已約落於2.5 V(VDD/2)的位置，達到無偏斜反相器的輸出特性。

In this research, the complementary metal-oxide-semiconductor high-electron-mobility transistors (CMOS-HEMTs) were integrated with the AlGaN/GaN Enhancement-mode (E-mode) and Depletion-mode (D-mode) transistors. Owing to the heterostructure of energy band, AlGaN/GaN HEMTs were born to have a great advantage of polarization-induced two dimensional electron gas (2DEG) channel to form a high-speed device.
Although the AlGaN/GaN HEMTs with the polarization induced two dimensional electron gas (2DEG) channel were generally fabricated as the D-mode transistors, Al-GaN/GaN enhancement-mode MOSHEMTs (E-mode MOSHEMTs) were still demanded to practical integrated circuits to simplify circuit design, improve safety capability, and reduce power consumption. Therefore, to fabricate the E-mode transistors, a gate-recessed structure and LiNbO3 ferroelectric charge trap gate stacked oxide layers were utilized in AlGaN/GaN E-mode MOSHEMTs.
Besides, to form the unskewed inverter, the current ratio () of E/D-mode transistors was adjusted with various etching depths in the AlGaN layer of the load type D-mode transistors. Compared to the typical tuning method, this PEC etching method is benefi-cial for scaling down the CMOS-HEMTs due to the matching size between the E-mode and D-mode MOSHEMTs. Finally, as the input signal was 5 V, the output swing of the resulting CMOS-HEMTs with the E/D-mode transistor current ratio () of 22 was 4.90 V. The noise margin high and low were about 1.99 V and 1.73 V, respectively. As to the voltage transfer curve (VTC), the corresponded VIN was about 2.5 V which be closer to VDD/2 (= 2.5 V) as the VOUT was 2.49 V, which revealed that the resulting CMOS-HEMTs with the  was 22 could be operated as an unskewed inverter.

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第四章
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