當資料在空氣中傳輸時，因為不可預期的雜訊干擾會導致資料錯誤，所以在資料傳送前會使用迴旋碼進行編碼，然後在接收端使用維特比演算法解碼。一般而言，在擔任手機核心的基頻晶片中，用維特比演算法實現的迴旋碼解碼器所需之功率消耗大約就佔了全部的三分之一，所以如果可以實現一個低功率的迴旋碼解碼器，可以大量地減少手機的消耗功率。
維特比演算法要求相當高的運算複雜度，所以導致其電路的功耗很大，所以近年來提出的低功率維特比演算法都是著重在減少運算複雜度，然而它們的缺點就是犧牲了解碼的正確率，使得位元錯誤率變高。與它們不同，我們提出的迴旋碼解碼器使用事先偵測的方式將接收到的位元分為受到雜訊干擾與沒有受到雜訊干擾兩種，若判斷為沒有受到雜訊干擾，所以不需要進行錯誤更正，只需使用一個低成本的解碼器對其解碼，且此電路只要求極少的功耗。若位元判斷為受到雜訊干擾，則是使用維特比解碼器進行解碼。
論文提出的低功率維特比解碼器是用Verilog 硬體描述語言進行電路設計並使用Artisan TSMC 0.18μm標準元件庫進行合成實現，其合成結果為63530個邏輯閘數，工作頻率則為200MHz。和其他維特比解碼器比較起來，我們提出的電路需要最少的功率消耗。

We may code data with convolutional code before data transmitted. And we don’t know whether the noises exist or not when data transmits in wireless system. And the receiver will use the Viterbi algorithm to decode. In general, the base band chip’s power dissipation occupies nearly 1/3 of all power consumptions in a mobile phone when the base band chip implemented with Viterbi algorithm. If we can propose a low power convolutional code decoder, we might reduce mobile phone's power consumption massively.
Viterbi algorithm has high power consumption because of the high complexity. In recent years, the low power Viterbi algorithm was proposed by reducing the operation complexity; however they sacrifice the bit error rate (BER). In the differences, we propose that the convolutional code decoder using preprocess divide the data into interfere with noises and do not interfere with noises. If not, it doesn’t need to do error correction, and only need using a low cost decoder to decode. The low cost decoder requested the only few power consumptions. If the data interfere with noise then we use the Viterbi decoder to decode the data.
The VLSI architecture of our viterbi decoder was implemented by using Verilog HDL. We used Design Vision to synthesize the design with TSMC’s 0.18μm cell library. The synthesis results show that our design occupies 63530 gate counts at the clock rate of 200 MHz. As compared with other Viterbi decoders, our design requires
the lowest power consumption.

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