本論文使用TSMC CMOS 0.18 µm製程設計應用於UWB接收機之射頻CMOS晶片及射頻前端電路的系統整合，包含3-5-GHz低電壓寬頻降頻混頻器與升頻混頻器、寬頻射頻接收機前端電路，及寬頻整合頻率合成器之CMOS射頻接收機。
3-5-GHz低電壓寬頻降頻混頻器採用切換轉導之雙平衡混頻架構。量測顯示: 在3-5 GHz的頻段內最高轉換增益為10-13 dB、最低雜訊介於7.5-8.3 dB、IIP3最大值約-7.5- -5 dBm、 input P1dB為-21- -16 dBm、LO-RF isolation大於50 dB、LO-IF isolation大於52 dB、RF-IF isolation大於50 dB、核心電路直流偏壓為1.2 V/2.1 mA，消耗功率為2.5 mW。3-5-GHz 升頻混頻器的部分採用折疊式之雙平衡混頻架構。量測顯示：最大轉換增益約5.3 dB，最大值OIP3約-0.5 dBm，LO-IF isolation 約為 37 dB, 直流消耗功率約 2.7 mW，操作電壓為Vdd 1.2 V。3-5-GHz 寬頻CMOS射頻接收機前端電路包含疊接架構之低雜訊放大器及I/Q降頻混頻器，並且使用單端輸入/雙端輸出的架構，省去巴倫平衡器設計以減少訊號衰減，量測顯示: 射頻接收機前端電路在3-5-GHz的頻段內最高轉換增益為18-27 dB、最低雜訊介於6-9.2 dB、IIP3最大值約-11- -5.5 dBm、LO-RF isolation大於51 dB、LO-IF isolation大於41 dB、RF-IF isolation大於10 dB、核心電路直流偏壓為1.8 V/26.2 mA、消耗功率為47.1 mW。3-5 GHz MB-OFDM UWB 整合頻率合成器之CMOS射頻接收機包含疊接組態之低雜訊放大器、結合電荷注入式之傳統單平衡式吉勃特混頻器及直接頻率合成架構之MB-OFDM UWB Mode-1 頻率合成器，量測顯示: 射頻接收機在3-5 GHz的頻段內最高轉換增益為17-24.1 dB、最低雜訊介於5.8-22.2 dB、IIP3最大值為-18- -12 dBm、RF-IF isolation約大於30 dB、核心電路直流偏壓為1.8 V/49 mA，消耗功率為88.2 mW。

This thesis presents the design on CMOS RFICs for MB-OFDM UWB RF Receiver. The RFICs are designed with TSMC 0.18 µm 1P6M standard CMOS fabrication process supplied. The first part presents 3-5-GHz low voltage broadband down-conversion and up-conversion mixers, the second part is 3-5-GHz broadband receiver front-end., and the third part is 3-5-GHz CMOS RF receiver integrated with frequency synthesizer for UWB MB-OFDM system.
The 3-5-GHz low voltage broadband CMOS down-conversion mixer employs a folded switched transconductor topology. Measured results are: a maximum conversion gain of 10-13 dB, minimum noise figure of 7.5-8.3 dB, maximum IIP3 of -7.5- -5 dBm, LO-RF isolation of about 50 dB, and a dc power only consumption of 2.5 mW at 1.2 V power supply. The 3-5-GHz low voltage broadband CMOS up-conversion mixer employs a folded switched topology. The mixer consists of a voltage-to-current (V-I) converter and a folded Gilbert switching quad. Measured results are: a maximum conversions gain of 5.3 dB, maximum OIP3 of -0.3 dBm, LO-IF isolation of about 37 dB, and a dc power only consumption of 2.7 mW at 1.2 V power supply.
The 3-5-GHz RF receiver front-end includes a LNA with a cascade topology and a I/Q mixer employing a single-balanced Gilbert cell topology. A pMOS current source is used to set transconductor and switching stage current independently. The quadrature LO signal generated by quadrature poly phase filter. Measured results are: a maximum conversion gain of 18-27 dB, minimum noise figure of 6-9.2 dB, maximum IIP3 of -11- -5.5 dBm, LO-RF isolation of about 51 dB, and a dc power only consumption of 47.1 mW at 1.8 V power supply. The 3-5-GHz CMOS RF receiver integrated with frequency synthesizer for UWB MB-OFDM system includes a LNA, a single-balanced Gilbert cell mixer and a MB-OFDM UWB CMOS mode-1 frequency synthesizer. Measured results are: a maximum conversion gain of 17-24.1 dB, minimum noise figure of 5.8-22.4 dB, maximum IIP3 of -18- -12 dBm, RF-IF isolation of about 30 dB, and a dc power only consumption of 88.2 mW at 1.8 V power supply.

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