現今，無線感測網路(wireless sensor networks)的實際應用已經具有相當的可行性。我們可以把這些感測節點放置在我們所想監測的環境或事物，然後透過這些節點所收集的資料進行分析。由於無線感測網路常常被使用在人們難以到達或者沒有任何人力存在的環境，我們必須依賴無線感測網路的回報來得知真正環境的狀況，因此這些感測節點所回報的資料的正確性便具有相當的重要性。本論文針對感測節點的容錯機制來設計一適合在硬體上實現的容錯決策演算法，並將其實現成電路。
在先前的研究[1]提出了一個當節點錯誤存在時的合作式錯誤容忍分散式決策融合機制(CSFD)，這個機制可以有效的分辨出錯誤的節點並且大大的改善決策融合的效能。雖然CSFD已經有很好的效能，但它在偵測錯誤節點過程中仍需要相當大的計算量，如指數、乘法/除法運算。在許多即時的無線感測網路的應用中，決策中心需要以特殊應用的積體電路(ASIC)方式來實現，並且整合在一可單獨運作的裝置中，所以我們需要一個具有低功率消秏和低硬體成本且低複雜度又有效的決策融合機制。在此論文中，我們提出了一個具有低複雜度的具錯誤容忍之決策融合機制(ACSFD)及它的超大型積體電路(VLSI)架構。由於此方法的計算複雜度較低，所以它是相當適合實現為硬體的。我們使用TSMC 0.18的製程來實現此電路，ACSFD電路的邏輯閘數(Gate Count)是9265，而它的核心大小(Core Size)為368×358μm^2。在不使用管線化(pipeline)設計的情況下，其工作頻率可達到102 MHz，且功率消秏僅為2.516 mW。模擬結果指出相較於傳統方法，ACSFD在錯誤容忍程度上具有較優異的效能。

The application of wireless sensor networks has been quite practicable nowadays. We can place the sensor nodes near to the things or environments which we want to monitor. We can use the message received from the sensor node to make decision fusion about the condition of the event. Therefore, the correctness of the data is very important. In the thesis, we have designed a sensor fault detection scheme suitable to hardware implementation.
A fault-tolerant distributed decision fusion in the presence of sensor faults via collaborative sensor fault detection (CSFD) was proposed in our previous research [1]. The scheme can identify the faulty nodes efficiently and improve the performance of the decision fusion significantly. It achieves very good performance at the expense of such extensive computations as exponent and multiplication/division in the detecting process. In many real-time WSN applications, the fusion center might be implemented with the ASIC and included in a standalone device. Therefore, a simple and efficient decision fusion scheme requiring lower hardware cost and power consumption is extremely desired. In this paper, we propose the approximated collaborative sensor fault detection (ACSFD) scheme and its VLSI architecture. Given the low circuit complexity, it is suitable for hardware implementation. The circuit of ACSFD contains 9265 gates and requires the core size of 368×358μm^2 by using TSMC 0.18 μm cell library. It can operate at the clock rate of 102 MHz with a power consumption of 2.516 mW. Simulation results indicate that ACSFD performs better in fault tolerance than the conventional approach.

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