以HfO₂為基礎之鐵電元件展現出作為非揮發性低溫記憶體的巨大潛力，但在低溫條件下可靠性問題，例如疲勞(fatigue)與記憶維持(retention)，仍然是其面臨的重要挑戰。本論文系統性地探討從平面結構到三維元件架構以及進階摻雜策略的HfO₂基鐵電場效電晶體(FeFETs)與電容元件，旨在實現在4 K低溫下穩定且可靠的操作。
首先，研究了以Si:HfO₂為基礎之平面型FeFETs在室溫下的特性，並嘗試不同閘極堆疊設計。研究發現，引入一層薄的矽覆蓋層(silicon capping layer)能透過氧捕捉(oxygen scavenging)作用並降低界面氧化層厚度，顯著提升元件的耐久性(endurance)與臨界電壓的穩定性。然而儘管存在上述優勢，元件仍持續出現記憶維持性能劣化與臨界電壓不穩定等問題。
隨後，研究進一步探討了無矽覆蓋層之平面型FeFETs在低溫環境下(4 K)的特性，成功展示了在低溫下記憶窗口(memory window)明顯擴大，並且有效抑制了電荷捕陷效應(charge trapping)。然而，基本限制因素，如持續存在的印記效應(imprint effect)及有限的耐久性，仍然是主要瓶頸。
接著，研究轉移至在低溫條件下的三維Fe-FinFET結構，實驗結果顯示出相較於平面元件更佳的次臨界特性(subthreshold characteristics)、降低的截止態漏電流(off-state leakage)以及更優越的靜電控制能力(electrostatic control)。儘管幾何結構的改進帶來上述優勢，但其耐久性依舊存在挑戰。
為了解決上述耐久性與可靠性等持續性問題，研究採取了將釔(Yttrium, Y)摻雜引入至HZO電容元件的方法。在4 K條件下，釔摻雜HZO電容器表現出高達10¹²次循環以上的無疲勞切換(fatigue-free switching)、卓越的極化維持能力(polarization retention)，並且對元件初期覺醒(wake-up)及印記效應(imprint)具有良好的抗性。這種摻雜策略顯著改善了鐵電元件在低溫條件下的可靠性。
綜合而言，本論文提出了全面且系統化的設計指引，旨在優化鐵電記憶體，以滿足未來量子計算(quantum computing)、類神經型計算系統(neuromorphic systems)以及太空電子(space electronics)等應用的需求；這些領域均要求鐵電元件在低溫條件下具備堅固的操作穩定性及卓越的可靠性。

HfO2-based Ferroelectric devices show significant promise for non-volatile cryogenic memory, yet reliability challenges such as fatigue and retention at low temperatures remain critical hurdles. This thesis systematically investigates HfO2-based FeFETs and capacitors from planar structures to three-dimensional device architectures and advanced doping strategies, focusing on achieving robust and reliable operation at 4 K. Initially, planar Si:HfO₂-based FeFETs were studied at room temperature with varying gate-stack designs. The introduction of a thin silicon capping layer notably enhanced endurance and threshold stability through oxygen scavenging and reduction of the interfacial oxide thickness. Despite these enhancements, issues like retention degradation and threshold voltage instability persisted. Subsequently, planar FeFETs without silicon capping were examined at cryogenic temperatures, demonstrating expanded memory windows and reduced charge trapping at 4 K. Nevertheless, fundamental limitations, including persistent imprint effects and limited endurance, remained problematic.
Transitioning to three-dimensional Fe-FinFET structures at cryogenic conditions provided substantial performance improvements, offering superior subthreshold characteristics, decreased off-state leakage, and enhanced electrostatic control compared to planar devices. Despite these geometric advantages, endurance limitations still posed challenges. To address these persistent issues, yttrium doping was introduced into HZO capacitors. At 4 K, these Y-doped capacitors exhibited fatigue-free switching over 10¹² cycles, excellent polarization retention, and immunity to wake-up and imprint effects. This approach significantly improved the cryogenic reliability of ferroelectric devices.
Ultimately, this work outlines comprehensive design guidelines to optimize Ferroelectric memories for future cryogenic applications in quantum computing, neuromorphic systems, and space electronics, where robust low-temperature operation and exceptional reliability are essential.

References for Chapter 1
[1] S. Alam, M. S. Hossain, S. R. S. Srinivasa, and A. Aziz, “Cryogenic memory technologies,” Nature Electronics, vol. 6, no. 3, pp. 185–198, 2023.
[2] S. Tannu, D. M. Carmean, and M. K. Qureshi, “Cryogenic-DRAM based memory system for scalable quantum computers: A feasibility study,” in Proc. Intl. Symp. Memory Systems (MemSys), 2017, pp. 189–196.
[3] L. Lang et al., “A low temperature functioning CoFeB/MgO-based perpendicular magnetic tunnel junction for cryogenic nonvolatile memory,” Appl. Phys. Lett., vol. 116, 022409, 2020.
[4] T. S. Böscke et al., "Ferroelectricity in hafnium oxide thin films," Appl. Phys. Lett., vol. 99, no. 10, p. 102903, 2011.
[5] A. J. Tan et al., "Ferroelectric HfO₂ Memory Transistors with High-κ Interfacial Layer and Write Endurance Exceeding 10¹⁰ Cycles," arXiv preprint arXiv:2103.08806, 2021
[6] Z. Wang et al., “Cryogenic characterization of a ferroelectric field-effect transistor,” Appl. Phys. Lett., vol. 116, 042902, 2020.
[7] K.-Y. Hsiang et al., “Cryogenic endurance of anti-ferroelectric and ferroelectric Hf₁₋ₓZrₓO₂ for quantum computing applications,” IEEE IRPS, 2023.
[8] R. W. J. Overwater, M. Babaie, and F. Sebastiano, “Cryogenic-Aware Forward Body Biasing in Bulk CMOS,” IEEE Electron Device Letters, vol. 45, no. 2, pp. 152–155, 2023.
[9] Y. Guo et al., “A Cryo-CMOS Quantum Computing Unit Interface Chipset in 28nm Bulk CMOS with Phase-Detection Based Readout and Phase-Shifter Based Pulse Generation,”in Proceedings of the 2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, pp. 476–478.
[10] L. Le Guevel et al., “A 22nm FD-SOI <1.2mW/Active-Qubit AWG-Free Cryo-CMOS Controller for Fluxonium Qubits,” in Proceedings of the 2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, pp. 473–475.
[11] F. Sebastiano et al., “Cryo-CMOS Circuits and Systems for Quantum Computing Applications,” IEEE Journal of Solid-State Circuits, vol. 53, no. 1, pp. 243–255, 2018.
[12] M. Castriotta, E. Prati, and G. Ferrari, “Cryogenic characterization and modeling of a CMOS floating-gate device for quantum control hardware,” arXiv preprint arXiv:2110.02315, 2021.
[13] J. Hasler et al., “Cryogenic Floating-Gate CMOS Circuits for Quantum Control,” IEEE Transactions on Quantum Engineering, vol. 2, pp. 1–14, 2021
[14] T. Sanuki et al., “Cryogenic Operation of 3D Flash Memory for Storage Performance Improvement and Bit Cost Scaling,” IEEE Transactions on Electron Devices, vol. 68, no. 12, pp. 6263–6268, 2021.
[15] S. Blonkowski and T. Cabout, “Bipolar resistive switching from liquid helium to room temperature,” J. Phys. D: Appl. Phys., vol. 48, no. 34, 345101, 2015.
[16] M. Lanza et al., “Conduction mechanisms, dynamics and stability in ReRAMs," Microelectronics Reliability, vol. 76–77, pp. 422–426, 2017.
[17] G. W. Burr et al., “Phase change memory technology,” Journal of Vacuum Science & Technology B, vol. 28, no. 2, pp. 223–262, 2010.
[18] C. Yau et al., “Hybrid Cryogenic Memory Cells for Superconducting Computing Applications,” IEEE Transactions on Applied Superconductivity, vol. 27, no. 4, p. 1301305, 2017.
[19] E. Garzón et al., “STT-MRAM Technology For Energy-Efficient Cryogenic Memory Applications,” IEEE Transactions on Nanotechnology, vol. 22, pp. 1–8, 2023.
[20] V. K. Semenov, Y. A. Polyakov, and S. K. Tolpygo, “Very Large Scale Integration of Josephson-Junction-Based Superconductor Random Access Memories,” arXiv preprint arXiv:1902.08302, 2019.
[21] K. Jackman and C. J. Fourie, “Flux Trapping Analysis in Superconducting Circuits,”IEEE Transactions on Applied Superconductivity, vol. 27, no. 4, pp. 1–5, 2017.
[22] Y. Zhou et al., "Sub-Nanosecond Switching of Si:HfO₂ Ferroelectric Field-Effect Transistors," Nano Letters, vol. 23, no. 2, pp. 1234–1240, 2023.
[23] M. Pérez-Bosch Quesada et al., "Forming and Resistive Switching of HfO₂-Based RRAM Devices at Cryogenic Temperature," IEEE Transactions on Electron Devices, vol. 70, no. 5, pp. 2390–2397, 2023.
[24] R. Huang et al., "Cryogenic Characterization of 180 nm CMOS Technology at 100 mK," arXiv preprint arXiv:2003.00207, 2020.
[25] A. Agarwal et al., “Y-HZO Capacitors Exhibiting Fatigue-Free (>10¹² cycles), Long Retention and Imprint-Immune Performance at 4 K,” IEEE EDL, Early access, 2025, Journal Article.
[26] G. L. Pearson and J. Bardeen, "Electrical Properties of Pure Silicon and Silicon Alloys Containing Boron and Phosphorus," Phys. Rev., vol. 75, no. 5, pp. 865–883, Mar. 1949.
[27] S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3rd ed., Hoboken, NJ, USA: Wiley, 2007.
[28] A. Beckers, F. Jazaeri, and C. Enz, "Physical Model of Low-Temperature to Cryogenic Threshold Voltage in MOSFETs," IEEE Transactions on Electron Devices, vol. 67, no. 10, pp. 4134–4141, Oct. 2020.
[29] E. Houwman, M. D. Nguyen, J. M. Dekkers, and G. Rijnders, "Intrinsic stability of ferroelectric and piezoelectric properties of epitaxial PbZr₀.₄₅Ti₀.₅₅O₃ thin films on silicon in relation to grain tilt," Applied Physics Letters, vol. 102, no. 6, p. 062902, 2013.
[30] A. Bhaskar, H.-Y. Chang, and T.-H. Chang, "Effect of Microwave Annealing Temperatures on Lead Zirconate Titanate Thin Films," Journal of the Korean Physical Society, vol. 51, no. 4, pp. 1321–1326, 2007.
[31] M. Pesic et al., "Physical Mechanisms Behind the Field-Cycling Behavior of HfO₂-Based Ferroelectric Capacitors," Advanced Functional Materials, vol. 26, no. 25, pp. 4601–4612, 2016.
[32] E. Yurchuk et al., "Origin of the Endurance Degradation in HfO₂-Based 1T Ferroelectric Memories," in Proc. IEEE Int. Reliability Physics Symp. (IRPS), 2014, pp. 2E.3.1–2E.3.6.
[33] A. Agarwal et al., "SiO₂ IL Scaling Through O Scavenging in Si-Channel n-FeFET With Si:HfO₂ Ferroelectric Layer," IEEE Transactions on Electron Devices, vol. 71, no. 8, pp. 4619–4627, 2024.
[34] N. Tasneem et al., " Remote Oxygen Scavenging of the Interfacial Oxide Layer in Ferroelectric Hafnium–Zirconium Oxide-Based Metal–Oxide–Semiconductor Structures.”ACS Applied Materials & Interfaces 2022 14 (38), 43897-43906.
[35] H. Choi, Y. H. Cho, S. H. Kim, K. Yang, and M. H. Park, “Hafnia-Based Ferroelectric Memory: Device Physics Strongly Correlated with Materials Chemistry,” J. Phys. Chem. Lett., vol. 15, no. 4, pp. 983–997, Feb. 2024.
[36] Y. Wei et al., “A rhombohedral ferroelectric phase in epitaxially strained Hf0.5Zr0.5O2 thin films,” Nature Mater, vol. 17, no. 12, pp. 1095–1100, Dec. 2018.
[37] P. Chandra and P. B. Littlewood, “A Landau Primer for Ferroelectrics,” Sep. 14, 2006, arXiv: arXiv:cond-mat/0609347.
[38] https://mangerij.github.io/ferret/theory/intro_LGD.html.
[39] A. K. Tagantsev, I. Stolichnov, N. Setter, J. S. Cross, and M. Tsukada, “Non Kolmogorov-Avrami switching kinetics in ferroelectric thin films,” Phys. Rev. B, vol. 66, no. 21, p. 214109, Dec. 2002.
[40] A. Agarwal et al., “Yttrium Doped Hf0.5Zr0.5O2 Based Ferroelectric Capacitor Exhibiting Fatigue Free (>1012 cycles), Long Retention, and Imprint Immune Performance at 4 K,” IEEE Electron Device Letters, pp. 1–1, 2025, doi: 10.1109/LED.2025.3562798.

References for Chapter 2
[1] A. Agarwal et al., "SiO₂ IL Scaling Through O Scavenging in Si-Channel n-FeFET With Si:HfO₂ Ferroelectric Layer," IEEE Transactions on Electron Devices, vol. 71, no. 8, pp. 4619–4627, 2024.
[2] K. Tomida et al., “Dielectric constant enhancement due to Si incorporation into HfO2,” Appl. Phys. Lett., vol. 89, no. 14, Oct. 2006, Art. no. 142902.
[3] N. Tasneem et al., " Remote Oxygen Scavenging of the Interfacial Oxide Layer in Ferroelectric Hafnium–Zirconium Oxide-Based Metal–Oxide–Semiconductor Structures.” ACS Applied Materials & Interfaces 2022 14 (38), 43897-43906.
[4] Y. B. Lee et al., "Oxygen-scavenging effects of added Ti layer in TiN gate of metal–ferroelectric–insulator–semiconductor capacitor with Al-doped HfO₂ ferroelectric film," Adv. Electron. Mater., vol. 8, no. 11, Art. no. 2200310, Nov. 2022.
[5] B. H. Kim et al., "Oxygen scavenging in HfZrOx-based n/p-FeFETs for switching voltage scaling and endurance/retention improvement," Adv. Electron. Mater., vol. 9, no. 5, Art. no. 2201257, May 2023.
[6] Y. Higashi et al., “Impact of charge trapping and depolarization on data retention using simultaneous P–V and I–V in HfO2-based ferroelectric FET,” IEEE Trans. Electron Devices, vol. 68, no. 9, pp. 4391–4396, Sep. 2021
[7] Y. Higashi et al., “Impact of charge trapping on imprint and its recovery in HfO2 based FeFET,” in IEDM Tech. Dig., Dec. 2019, p. 15.
[8] R. Ichihara et al., “Re-examination of vth window and reliability in HfO2 FeFET based on the direct extraction of spontaneous polar- ization and trap charge during memory operation,” in Proc. IEEE Symp. VLSI Technol., Jun. 2020, pp. 1–2.
[9] S. Deng et al., “Unraveling the dynamics of charge trapping and de- trapping in ferroelectric FETs,” IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1503–1511, Mar. 2022.
[10] C. Su et al., “New insights into memory window of ferroelectric FET impacted by read opera- tions with awareness of polarization switching dynamics,” IEEE Trans. Electron Devices, vol. 69, no. 9, pp. 5310–5315, Sep. 2022.
[11] A. K. Tagantsev et al., “Non–Kolmogorov–Avrami switching kinetics in ferroelectric thin films,” Phys. Rev. B, Condens. Matter, vol. 66, no. 21, Dec. 2002, Art. no. 214109.
[12] E. Yurchuk et al., “Charge-trapping phenomena in HfO2-based FeFET- type nonvolatile memories,” IEEE Trans. Electron Devices, vol. 63, no. 9, pp. 3501–3507, Sep. 2016.
[13] K. Ni et al., “Critical role of interlayer in Hf0.5Zr0.5O2 ferro- electric FET nonvolatile memory performance,” IEEE Trans. Electron Devices, vol. 65, no. 6, pp. 2461–2469, Jun. 2018.
[14] S. Zhao et al., “Experimental extraction and simulation of charge trap- ping during endurance of FeFET with TiN/HfZrO/SiO2/Si (MFIS) gate structure,” IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1561–1567, Mar. 2022.
[15] P. Cai et al., “Deep understanding of reliability in HF-based FeFET during bipolar pulse cycling: Trap profiling for read-after-write delay and memory window degradation,” in IEDM Tech. Dig., Dec. 2022, p. 32.
[16] K. Toprasertpong et al., “Memory window in ferroelectric field-effect transistors: Analytical approach,” IEEE Trans. Electron Devices, vol. 69, no. 12, pp. 7113–7119, Dec. 2022.
[17] K. Toprasertpong et al., “On the strong coupling of polarization and charge trapping in HfO2/Si-based ferroelectric field- effect transistors: Overview of device operation and reliability,” Appl. Phys. A, Solids Surf., vol. 128, no. 12, p. 1114, Dec. 2022.

References for Chapter 3
[1] S. Alam et al., “Cryogenic memory technologies,” Nature Electronics, vol. 6, no. 3, pp. 185–189, Mar. 2023.
[2] M. M. Islam et al., “A review of cryogenic neuromorphic hardware,” J. Appl. Phys., vol. 133, no. 7, p. 070701, Feb. 2023.
[3] K.-Y. Hsiang et al., “Cryogenic Endurance of Anti-ferroelectric and Ferroelectric Hf₁₋ₓZrₓO₂ for Quantum Computing Applications,” in Proc. IEEE IRPS, Monterey, CA, USA, 2023, pp. 1–4.
[4] J. Hur et al., “Characterizing Ferroelectric Properties of Hf₀.₅Zr₀.₅O₂ from Deep-Cryogenic Temperature (4 K) to 400 K,” IEEE J. Explor. Solid-State Comput. Devices Circuits, vol. 7, no. 2, pp. 168–174, Dec. 2021.
[5] Z. Wang et al., “Cryogenic characterization of a ferroelectric field-effect transistor,” Appl. Phys. Lett., vol. 116, no. 4, p. 042902, Jan. 2020.
[6] S. G. Kirtania et al., “Cold-FeFET as Embedded Non-Volatile Memory with Unlimited Cycling Endurance,” in Proc. IEEE VLSI Technology & Circuits Symp., Kyoto, Japan, Jun. 2023, pp. 1–2.
[7] A. Agarwal et al., “Study of Endurance Performance of SiO₂ Interfacial Layer Scaling Through O₂ Scavenging in Si Channel n-FeFET With Si:HfO₂ Ferroelectric Layer,” IEEE Trans. Electron Devices, vol. 71, no. 8, pp. 4619–4626, Aug. 2024.
[8] A. Agarwal et al., “Yttrium Doped Hf₀.₅Zr₀.₅O₂ Ferroelectric Capacitor Exhibiting Fatigue-Free (>10¹² cycles), Long Retention, and Imprint-Immune Performance at 4 K,” IEEE Electron Device Lett. (early access), vol. 46, 2025.
[9] T. Ma, et al, IEEE Electron Device Letters, 23, 386, 2002.
[10] E. Yurchuk, et al, IEEE Trans. Electron Devices, 63, 3501, 2016.
[11] P. Cai, et al, IEEE IEDM Tech. Dig.,32.2.1, 2022.
[12] A. J. Tan, et al, 2020 IEEE Symposium on VLSI Technology, 978-1-7281-6460-1.
[13] William Cheng-Yu Ma, et al, 2022 Semicond.Sci.Technol., 37 045003.
[14] K. Ni, et al, IEEE Trans. Electron Devices, 65, 2461, 2018.
[15] C. Su, et al, IEEE Trans. Electron Devices, 69, 5310, 2022.

References for Chapter 4
[1] S. Alam, M. S. Hossain, S. R. Srinivasa, and A. Aziz, “Cryogenic memory technologies,” Nat. Electron., vol. 6, no. 3, Art. no. 3, Mar. 2023, doi: 10.1038/s41928-023-00930-2.
[2] J. Hur, Y.-C. Luo, Z. Wang, S. Lombardo, A. I. Khan, and S. Yu, “Characterizing Ferroelectric Properties of Hf0.5Zr0.5O2 From Deep-Cryogenic Temperature (4 K) to 400 K,” IEEE J. Explor. Solid-State Comput. Devices Circuits, vol. 7, no. 2, pp. 168–174, Dec. 2021, doi: 10.1109/JXCDC.2021.3130783.
[3] K.-Y. Hsiang et al., “Cryogenic Endurance of Anti-ferroelectric and Ferroelectric Hf1-xZrXO2 for Quantum Computing Applications,” in 2023 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA: IEEE, Mar. 2023, pp. 1–4. doi: 10.1109/IRPS48203.2023.10118311.
[4] M. M. Islam, S. Alam, M. S. Hossain, K. Roy, and A. Aziz, “A review of cryogenic neuromorphic hardware,” J. Appl. Phys., vol. 133, no. 7, p. 070701, Feb. 2023, doi: 10.1063/5.0133515.
[5] Z. Wang et al., “Cryogenic characterization of a ferroelectric field-effect-transistor,” Appl. Phys. Lett., vol. 116, no. 4, p. 042902, Jan. 2020, doi: 10.1063/1.5129692.
[6] S. G. Kirtania, K. A. Aabrar, A. I. Khan, S. Yu, and S. Datta, “Cold-FeFET as Embedded Non-Volatile Memory with Unlimited Cycling Endurance,” in 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan: IEEE, Jun. 2023, pp. 1–2. doi: 10.23919/VLSITechnologyandCir57934.2023.10185382.
[7] S.-H. Kuk et al., “Examination of Ferroelectric FET for ‘Cold’ Non-volatile Memory,” IEEE Trans. Electron Devices, pp. 1–6, 2023, doi: 10.1109/TED.2023.3278611.
[8] Z. Krivokapic et al., “14nm Ferroelectric FinFET Technology with Steep Subthreshold Slope for Ultra Low Power Applications,” in 2017 IEEE International Electron Devices Meeting (IEDM), Dec. 2017, pp. 15.1.1–15.1.4, doi: 10.1109/IEDM.2017.8268393.
[9] C.-J. Su et al., “Nano-scaled Ge FinFETs with Low Temperature Ferroelectric HfZrOx on Specific Interfacial Layers Exhibiting 65% S.S. Reduction and Improved ION,” in 2017 Symposium on VLSI Technology, Kyoto, Japan: IEEE, Jun. 2017, pp. T152–T153, doi: 10.23919/VLSIT.2017.7998159.
[10] M. H. Lin et al., “On the Electrical Characteristics of Ferroelectric FinFET Using Hafnium Zirconium Oxide with Optimized Gate Stack,” ECS J. Solid State Sci. Technol., vol. 7, no. 11, p. P640, Oct. 2018, doi: 10.1149/2.0091811jss.
[11] M. -J. Tsai et al., "Investigation of 5-nm-Thick Hf0.5Zr0.5O2 Ferroelectric FinFET Dimensions for Sub-60-mV/Decade Subthreshold Slope," in IEEE Journal of the Electron Devices Society, vol. 7, pp. 1033-1037, 2019, doi: 10.1109/JEDS.2019.2942381.

References for Chapter 5
[1] S. Alam, M. S. Hossain, S. R. Srinivasa, and A. Aziz, “Cryogenic memory technologies,” Nat. Electron., vol. 6, no. 3, Art. no. 3, Mar. 2023, doi: 10.1038/s41928-023-00930-2.
[2] T. S. Böscke, J. Müller, D. Bräuhaus, U. Schröder, and U. Böttger, “Ferroelectricity in hafnium oxide thin films,” Appl. Phys. Lett., vol. 99, no. 10, p. 102903, Sep. 2011, doi: 10.1063/1.3634052.
[3] D. Lehninger et al., “Back-End-of-Line Compatible Low-Temperature Furnace Anneal for Ferroelectric Hafnium Zirconium Oxide Formation,” Phys. Status Solidi A, vol. 217, no. 8, p. 1900840, 2020, doi: 10.1002/pssa.201900840.
[4] S. H. Park, J. Y. Kim, J. Y. Song, and H. W. Jang, “Overcoming Size Effects in Ferroelectric Thin Films,” Adv. Phys. Res., vol. 2, no. 6, p. 2200096, 2023, doi: 10.1002/apxr.202200096.
[5] J. Müller, P. Polakowski, S. Mueller, and T. Mikolajick, “Ferroelectric Hafnium Oxide Based Materials and Devices: Assessment of Current Status and Future Prospects,” ECS J. Solid State Sci. Technol., vol. 4, no. 5, pp. N30–N35, 2015, doi: 10.1149/2.0081505jss.
[6] J. Müller et al., “Ferroelectricity in yttrium-doped hafnium oxide,” J. Appl. Phys., vol. 110, no. 11, p. 114113, Dec. 2011, doi: 10.1063/1.3667205.
[7] A. M. Walke et al., “Electrical Investigation of Wake-Up in High Endurance Fatigue-Free La and Y Doped HZO Metal–Ferroelectric–Metal Capacitors,” IEEE Trans. Electron Devices, vol. 69, no. 8, pp. 4744–4749, Aug. 2022, doi: 10.1109/TED.2022.3186869.
[8] L. Zhao, J. Liu, and Y. Zhao, “Systematic studies of the effects of group-III dopants (La, Y, Al, and Gd) in Hf0.5Zr0.5O2 ferroelectrics by ab initio simulations,” Appl. Phys. Lett., vol. 119, no. 17, p. 172903, Oct. 2021, doi: 10.1063/5.0066169.
[9] J. Y. Kim et al., “High-Performance Ferroelectric Thin Film Transistors with Large Memory Window Using Epitaxial Yttrium-Doped Hafnium Zirconium Gate Oxide,” ACS Appl. Mater. Interfaces, vol. 16, no. 15, pp. 19057–19067, Apr. 2024, doi: 10.1021/acsami.3c16427.
[10] Y. Oh, S. W. Lee, J.-H. Choi, S.-E. Ahn, H.-B. Kim, and J.-H. Ahn, “Yttrium Doping Effects on Ferroelectricity and Electric Properties of As-Deposited Hf1−xZrxO2 Thin Films via Atomic Layer Deposition,” Nanomaterials, vol. 13, no. 15, Art. no. 15, Jan. 2023, doi: 10.3390/nano13152187.
[11] T. Shimizu et al., “The demonstration of significant ferroelectricity in epitaxial Y-doped HfO2 film,” Sci. Rep., vol. 6, no. 1, p. 32931, Sep. 2016, doi: 10.1038/srep32931.
[12] J. Hur, Y.-C. Luo, Z. Wang, S. Lombardo, A. I. Khan, and S. Yu, “Characterizing Ferroelectric Properties of Hf0.5Zr0.5O2 From Deep-Cryogenic Temperature (4 K) to 400 K,” IEEE J. Explor. Solid-State Comput. Devices Circuits, vol. 7, no. 2, pp. 168–174, Dec. 2021, doi: 10.1109/JXCDC.2021.3130783.
[13] K.-Y. Hsiang et al., “Cryogenic Endurance of Anti-ferroelectric and Ferroelectric Hf1-xZrXO2 for Quantum Computing Applications,” in 2023 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA: IEEE, Mar. 2023, pp. 1–4. doi: 10.1109/IRPS48203.2023.10118311.
[14] M. M. Islam, S. Alam, M. S. Hossain, K. Roy, and A. Aziz, “A review of cryogenic neuromorphic hardware,” J. Appl. Phys., vol. 133, no. 7, p. 070701, Feb. 2023, doi: 10.1063/5.0133515.
[15] H. Bohuslavskyi, K. Grigoras, M. Ribeiro, M. Prunnila, and S. Majumdar, “Ferroelectric Hf0.5Zr0.5O2 for Analog Memory and In-Memory Computing Applications Down to Deep Cryogenic Temperatures,” Adv. Electron. Mater., vol. n/a, no. n/a, p. 2300879, Apr. 2024, doi: 10.1002/aelm.202300879.
[16] M. H. Park et al., “Origin of Temperature-Dependent Ferroelectricity in Si-Doped HfO2,” Adv. Electron. Mater., vol. 4, no. 4, p. 1700489, 2018, doi: 10.1002/aelm.201700489.
[17] J. Xu et al., “Characterizing polarization switching kinetics of ferroelectric Hf0.5Zr0.5O2 at cryogenic temperature,” J. Appl. Phys., vol. 136, no. 10, p. 104101, Sep. 2024, doi: 10.1063/5.0218693.
[18] M. Karthik Ram, H. Dahlberg, and L.-E. Wernersson, “Cryogenic Ferroelectricity of HZO Capacitors on a III–V Semiconductor,” IEEE Electron Device Lett., vol. 45, no. 10, pp. 1827–1830, Oct. 2024, doi: 10.1109/LED.2024.3448378.
[19] Z. Yang et al., “Structural characteristics and polarization switching behaviors in HfO2-ZrO2 ferroelectric nanolaminates,” J. Alloys Compd., vol. 1004, p. 175909, Nov. 2024, doi: 10.1016/j.jallcom.2024.175909.
[20] D. Zhang et al., “Unveiling Cryogenic Performance (4 to 300 K) Towards Ultra-Thin Ferroelectric HZO: Novel Kinetic Barrier Engineering and Underlying Mechanism,” in 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Jun. 2024, pp. 1–2. doi: 10.1109/VLSITechnologyandCir46783.2024.10631318.
[21] S. Starschich, S. Menzel, and U. Böttger, “Evidence for oxygen vacancies movement during wake-up in ferroelectric hafnium oxide,” Appl. Phys. Lett., vol. 108, no. 3, p. 032903, Jan. 2016, doi: 10.1063/1.4940370.
[22] S. Wu et al., “Reliable ferroelectricity down to cryogenic temperature in wake-up free Hf0.5Zr0.5O2 thin films by thermal atomic layer deposition,” J. Semicond., vol. 45, no. 3, p. 032301, 2024, doi: 10.1088/1674-4926/45/3/032301.
[23] M. I. Popovici et al., “High-Endurance Ferroelectric (La, Y) and (La, Gd) Co-Doped Hafnium Zirconate Grown by Atomic Layer Deposition,” ACS Appl. Electron. Mater., vol. 4, no. 4, pp. 1823–1831, Apr. 2022, doi: 10.1021/acsaelm.2c00063.
[24] A. Chouprik et al., “Wake-Up in a Hf0.5Zr0.5O2 Film: A Cycle-by-Cycle Emergence of the Remnant Polarization via the Domain Depinning and the Vanishing of the Anomalous Polarization Switching,” ACS Appl. Electron. Mater., vol. 1, no. 3, pp. 275–287, Mar. 2019, doi: 10.1021/acsaelm.8b00046.
[25] S. S. Fields et al., “Phase-Exchange-Driven Wake-Up and Fatigue in Ferroelectric Hafnium Zirconium Oxide Films,” ACS Appl. Mater. Interfaces, vol. 12, no. 23, pp. 26577–26585, Jun. 2020, doi: 10.1021/acsami.0c03570.
[26] L. Vandelli, A. Padovani, L. Larcher, and G. Bersuker, “Microscopic Modeling of Electrical Stress-Induced Breakdown in Poly-Crystalline Hafnium Oxide Dielectrics,” IEEE Trans. Electron Devices, vol. 60, no. 5, pp. 1754–1762, May 2013, doi: 10.1109/TED.2013.2255104.
[27] F. Mehmood et al., “Bulk Depolarization Fields as a Major Contributor to the Ferroelectric Reliability Performance in Lanthanum Doped Hf0.5Zr0.5O2 Capacitors,” Adv. Mater. Interfaces, vol. 6, no. 21, p. 1901180, 2019, doi: 10.1002/admi.201901180.
[28] M. D. Henry, S. W. Smith, R. M. Lewis, and J. F. Ihlefeld, “Stabilization of ferroelectric phase of Hf0.58Zr0.42O2 on NbN at 4 K,” Appl. Phys. Lett., vol. 114, no. 9, p. 092903, Mar. 2019, doi: 10.1063/1.5052435.
[29] P. Nukala et al., “Reversible oxygen migration and phase transitions in hafnia-based ferroelectric devices,” Science, vol. 372, no. 6542, pp. 630–635, May 2021, doi: 10.1126/science.abf3789.
[30] Y. Zheng et al., “Atomic-scale characterization of defects generation during fatigue in ferroelectric Hf0.5Zr0.5O2 films: vacancy generation and lattice dislocation,” in 2021 IEEE International Electron Devices Meeting (IEDM), Dec. 2021, p. 33.5.1-33.5.4. doi: 10.1109/IEDM19574.2021.9720565.
[31] A. K. Tagantsev, I. Stolichnov, E. L. Colla, and N. Setter, “Polarization fatigue in ferroelectric films: Basic experimental findings, phenomenological scenarios, and microscopic features,” J. Appl. Phys., vol. 90, no. 3, pp. 1387–1402, Aug. 2001, doi: 10.1063/1.1381542.
[32] J. Lee et al., “Role of oxygen vacancies in ferroelectric or resistive switching hafnium oxide,” Nano Converg., vol. 10, no. 1, p. 55, Dec. 2023, doi: 10.1186/s40580-023-00403-4.
[33] A. M. Walke, S. Clima, M. I. Popovici, and J. V. Houdt, “Understanding Anti-ferroelectric Behavior and Wake-up in La Doped HZO Metal-FerroelectricMetal Capacitors Using Nucleation Limited Switching Model,” in 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), Sep. 2024, pp. 565–568. doi: 10.1109/ESSERC62670.2024.10719525.
[34] Y. Yun et al., “Intrinsic ferroelectricity in Y-doped HfO2 thin films,” Nat. Mater., vol. 21, no. 8, pp. 903–909, Aug. 2022, doi: 10.1038/s41563-022-01282-6.
[35] F. P. G. Fengler et al., “Domain Pinning: Comparison of Hafnia and PZT Based Ferroelectrics,” Adv. Electron. Mater., vol. 3, no. 4, p. 1600505, 2017, doi: 10.1002/aelm.201600505.
[36] Y. Xing et al., “Improved Ferroelectricity in Cryogenic Phase Transition of Hf0.5Zr0.5O2,” IEEE J. Electron Devices Soc., vol. 10, pp. 996–1002, 2022, doi: 10.1109/JEDS.2022.3218004.
[37] Z. Wang et al., “Cryogenic characterization of a ferroelectric field-effect-transistor,” Appl. Phys. Lett., vol. 116, no. 4, p. 042902, Jan. 2020, doi: 10.1063/1.5129692.

References for Chapter 6
[1] A. Agarwal, A. M. Walke, N. Ronchi, K. H. Kao, and J. Van Houdt, “Study of Endurance Performance of SiO₂ Interfacial Layer Scaling Through O Scavenging in Si Channel n-FeFET With Si:HfO₂ Ferroelectric Layer,” IEEE Trans. Electron Devices, vol. 71, no. 8, pp. 4619–4625, 2024.
[2] Z. Wang et al., “Cryogenic characterization of a ferroelectric field-effect transistor,” Appl. Phys. Lett. 116, 042902 (2020).
[3] M. -J. Tsai et al., "Investigation of 5-nm-Thick Hf0.5Zr0.5O2 Ferroelectric FinFET Dimensions for Sub-60-mV/Decade Subthreshold Slope," in IEEE Journal of the Electron Devices Society, vol. 7, pp. 1033-1037, 2019.
[4] A. Agarwal et al., “Yttrium Doped Hf0.5Zr0.5O2 Based Capacitors Exhibiting Fatigue-Free (>10¹² cycles), Long Retention and Imprint-Immune Performance at 4 K,” IEEE EDL, Early access, 2025, Journal Article
[5] M. Lederer et al., "Enhanced reliability and trapping behavior in ferroelectric FETs under cryogenic conditions," 2024 IEEE International Memory Workshop (IMW), Seoul, Korea, Republic of, 2024, pp. 1-4
[6] S. De et al., “Neuromorphic Computing with Ferroelectric FinFETs in the Presence of Temperature, Process Variation, Device Aging and Flicker Noise,” arXiv:2103.13302 [cs.ET], 2022.
[7] S. S. Parihar et al. “Modeling and Benchmarking 5nm Ferroelectric FinFET from Room Temperature down to Cryogenic Temperatures,” TechRxiv. June 07, 2023
[8] D. Kim et al., “Low-Temperature Nanosecond Laser Process of HZO-IGZO FeFETs toward Monolithic 3D System on Chip Integration,” Adv. Sci. 2024, 11, 2401250.