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研究生: 鍾遠哲
Chung, Yuan-Che
論文名稱: 以氮化鋁鎵/氮化鎵高電子遷移率電晶體研製單一基板整合之邏輯電路
Monolithically integrated AlGaN/GaN HEMTs Logic Circuits
指導教授: 王永和
Wang, Yeong-Her
學位類別: 碩士
Master
系所名稱: 智慧半導體及永續製造學院 - 關鍵材料學位學程
Program on Key Materials
論文出版年: 2024
畢業學年度: 112
語文別: 英文
論文頁數: 99
中文關鍵詞: 氮化鋁鎵/氮化鎵異質接面場效應電晶體n通道元件p通道元件蝕刻時間氧化層表面處理氮化鎵邏輯元件氮化鎵相反器
外文關鍵詞: AlGaN/GaN high electron mobility transistor (HEMT), E-mode GaN device, E-mode p-channel GaN device, etching time, surface treatment, oxide layer, GaN DCFL/CMOS logic devices, GaN-based inverter
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  • 氮化鎵(GaN)高電子遷移率晶體管(HEMTs)展現出優異的高頻和高功率操作特性。然而,在GaN高頻和高功率器件中,通常會結合矽基周圍邏輯電路進行打線及封裝。在本文中,我們專注於開發基於GaN基板的邏輯電路,旨在通過將其與高頻和高功率GaN元件集成,來提高器件的可靠性。本研究旨在利用AlGaN/GaN高電子遷移率晶體管(HEMTs)開發高效率的邏輯電路。為此,我們開發了兩種類型的邏輯電路:DCFL和CMOS邏輯電路。
    在第一部分中,使用適度和積極閘極蝕刻處理的耗盡型和增強型AlGaN/GaN HEMTs集成到單個晶片中,形成了DCFL反相器。通過TMAH溶液表面處理和閘極蝕刻後的長時間氮氣退火進一步減少了界面陷阱。在2V的供電電壓下,E/D反相器顯示出1.7V的輸出邏輯擺幅、0.89V的低邏輯噪聲容限、0.81V的高邏輯噪聲容限,以及14.3 V/V的高電壓增益,元件表現出很好的抗雜訊能力。
    在第二部分中,使用閘極蝕刻處理的p通道和n通道增強型器件集成到單個晶片中,此研究開發了CMOS原型並確定了未來改進的方向。GaN p-channel HEMT 在閘極蝕刻和閘極氧化層的處理下,測得更高的閘極閾值電壓(Vth)(-0.3V)和更低的閘極漏電流(Ig), 這些改良進一步提升p-channel的可行性。

    GaN high electron mobility transistors (HEMTs) exhibit excellent high-frequency and high-power operation characteristics. However, in GaN high-frequency and high-power devices, wire bonding packaging is typically combined with silicon-based peripheral logic circuits. In this paper, we focus on developing GaN-based substrate logic circuits with the aim of enhancing the reliability of devices by integrating them with high-frequency and high-power GaN components. This work aims to develop high-efficiency logic circuits using AlGaN/GaN-based high electron mobility transistors (HEMTs). To achieve this, we developed two types of logic circuits: DCFL and CMOS logic circuits.
    In the first part, depletion-mode and enhancement-mode AlGaN/GaN HEMTs using moderate and aggressive gate recess treatment were integrated into a single chip, forming a DCFL inverter. The TMAH solution surface treatment and prolonged nitrogen annealing after gate recess etching further reduced interface traps. At a supply voltage of 2V, the E/D inverter showed an output logic swing of 1.7V, a good logic-low noise margin of 0.89V, a logic-high noise margin of 0.81V, and a high voltage gain of 14.3 V/V.
    In the second part, p-channel and n-channel enhancement-mode devices with gate etching treatment were integrated into a single chip. This study developed a CMOS prototype and identified directions for future improvements. GaN p-channel HEMTs with gate-recess and gate oxide were measured to have higher threshold voltage (Vth) (-0.3V) and lower gate current (Ig). These improvements further enhance the feasibility of p-channel devices.

    摘要 III Monolithically intrgrated AlGaN/GaN HEMTs Logic Circuits 4 Abstract 4 Table of Contents 6 List of Figures 9 List of Tables XIII CHAPTER 1 Introduction 1 1.1 Background 1 1.1.1 Background 1 1.1.2 Wide-Bandgap Materials and advantages of GaN 2 1.2 Motivation 5 1.2.1 Design Concept 5 1.2.2 Design Analysis 6 1.2.3 Short-term and Long-term goals 6 1.3 Organization 8 CHAPTER 2 Basic Theory 8 2.1 GaN HEMTs Polarization Effect 8 2.1.1 spontaneous polarization 9 2.1.2 piezoelectric polarization 11 2.2 Contact of Metal and Simeconductor 14 2.2.1 N-type Ohmic Metal-Semiconductor contact : 14 2.2.2 N-type Schottky Metal-Semiconductor contact : 14 2.2.3 P-type Ohmic Metal-Semiconductor contact : 15 2.2.4 P-type Schottky Metal-Semiconductor contact : 15 2.3 Transmission Line Model measurement 16 2.4 Annealing 19 2.4.1 N-type ohmic contact annealing under N2 ambient : 19 2.4.2 P-type ohmic contact annealing under O2 ambient: 20 2.4.3 Postmetallization annealing (PMA) on interface properties of Al2O3/GaN structures: 22 2.5 Gate-recessed MIS-FET with dielectric lyaer: 22 2.6 Analysis of Logic Circuits 24 2.6.1 Analysis of Si-based Static CMOS 24 2.6.2 Analysis of Si-based Pseudo-NMOS 26 2.6.3 Pros and Cons 28 2.6.4 CMOS 28 2.6.5 Pseudo-nmos 29 CHAPTER 3 Experiments 30 3.1 Design of photomasks 30 3.2 DCFL Logic Circuits Device fabrication 31 3.3 N-type E-mode GaN HEMT process 32 3.3.1 Sample Cutting and Cleaning 32 3.3.2 Mesa Isolation 32 3.3.3 S/D Metal Deposition 34 3.3.4 Gate-Recess 36 3.3.5 Gate Metal Deposition 38 3.3.6 E/D-mode GaN HEMTs integration process 40 3.3.7 Schematic Procedures 42 3.4 CMOS Logic Circuits fabrication 44 3.5 n-type E-mode GaN HEMT process 45 3.5.1 Sample Cutting and Cleaning 45 3.5.2 P-GaN Removal 45 3.5.3 Mesa Isolation 46 3.5.4 S/D Metal Deposition 47 3.5.5 Gate-Recess 50 3.5.6 Gate Metal Deposition 52 3.5.7 Schematic Procedures 54 3.5.8 p-channel HFET process[45] 55 3.5.9 Sample Cleaning 55 3.5.10 S/D Metal Stack Formation 56 3.5.11 Mesa Isolation 58 3.5.12 Gate Recess Etching and Surface Treatment 59 3.5.13 Gate Metal Stack Formation 60 3.5.14 Schematic Procedures 61 CHAPTER 4 Results and Discussion 63 4.1 DCFL logic circuits analysis 63 4.1.1 Transmission Electron Microscopy 63 4.1.2 Energy-Dispersive X-ray Spectroscopy 63 4.1.3 Electrical Characterization 66 4.1.4 TLM measurement 66 4.1.5 Output and Transfer Characteristics of Driver (ID-VD& ID-VG) 66 4.1.6 Gate Leakage Current of Driver (IG-VG) 68 4.1.7 Output Characteristics of Load (ID-VD) 68 4.1.8 Transfer curve of DCFL inverter 69 4.1.9 Ltspice simulation on Current ratio β of DCFL inverter 71 4.2 CMOS logic circuits analysis 73 4.2.1 P-channel TLM measurement 73 4.2.2 P-channel Output Characteristics (ID-VD) 74 4.2.3 Transfer Characteristics (ID-VG) 75 4.2.4 Gate Leakage Current (IG-VG) 75 4.2.5 N-channel TLM measurement 76 4.2.6 N-channel Output Characteristics (ID-VD) and Transfer Characteristics (ID-VG) 77 4.2.7 CMOS schottky type with wird-bonding 77 4.2.8 CMOS MOS-type single chip integrated 78 4.3 I-V characteristics Comparison table of all works 81 CHAPTER 5 Conclusion 82 CHAPTER 6 FUTURE WORK 82 References 83

    1. Yuk, K., G. Branner, and C. Cui. Future directions for GaN in 5G and satellite communications. in 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS). 2017. IEEE.
    2. Su, M., C. Chen, and S. Rajan, Prospects for the application of GaN power devices in hybrid electric vehicle drive systems. Semiconductor Science and Technology, 2013. 28(7): p. 074012.
    3. Cabizza, S., G. Spiazzi, and L. Corradini, GaN-Based Isolated Resonant Converter as a Backup Power Supply in Automotive Subnets. IEEE Transactions on Power Electronics, 2023. 38(6): p. 7362-7373.
    4. Al Hadi, A., et al., Hardware Evaluation for GaN-Based Single-Phase Five-Level Inverter. IEEE Access, 2023.
    5. Zheng, Z., et al., Gallium nitride-based complementary logic integrated circuits. Nature electronics, 2021. 4(8): p. 595-603.
    6. Pan, C., et al., Monolithically Integrated Logic Circuits based on p-NiO gated E-mode GaN HEMTs. IEEE Electron Device Letters, 2023.
    7. Ghose, S., et al., Growth and characterization of β-Ga2O3 thin films by molecular beam epitaxy for deep-UV photodetectors. Journal of Applied Physics, 2017. 122(9).
    8. Cheng, L., J.-Y. Yang, and W. Zheng, Bandgap, mobility, dielectric constant, and baliga’s figure of merit of 4H-SiC, GaN, and β-Ga2O3 from 300 to 620 K. ACS Applied Electronic Materials, 2022. 4(8): p. 4140-4145.
    9. Nikolaev, V., et al., Epitaxial growth of (2 01) β-Ga2O3 on (0001) sapphire substrates by halide vapour phase epitaxy. Materials Science in Semiconductor Processing, 2016. 47: p. 16-19.
    10. Keshmiri, N., et al., Current status and future trends of GaN HEMTs in electrified transportation. IEEE Access, 2020. 8: p. 70553-70571.
    11. Zhang, Y., et al., MOCVD grown epitaxial β-Ga2O3 thin film with an electron mobility of 176 cm2/V s at room temperature. APL Materials, 2019. 7(2).
    12. Ghosh, K. and U. Singisetti, Ab Initio Velocity-Field Curves in Monoclinic(eta)-Ga extsubscript {2} O extsubscript {3}. arXiv preprint arXiv:1612.03126, 2016.
    13. Chow, T.P. Wide bandgap semiconductor power devices for energy efficient systems. in 2015 IEEE 3rd Workshop on Wide Bandgap Power Devices and Applications (WiPDA). 2015. IEEE.
    14. Jiang, P., et al., Three-dimensional anisotropic thermal conductivity tensor of single crystalline β-Ga2O3. Applied physics letters, 2018. 113(23).
    15. Croce, G., et al., BCD Process Technologies, in Springer Handbook of Semiconductor Devices. 2022, Springer. p. 67-116.
    16. Bader, S.J., et al., Prospects for wide bandgap and ultrawide bandgap CMOS devices. IEEE Transactions on Electron Devices, 2020. 67(10): p. 4010-4020.
    17. Zheng, Z., et al. Enhancement-mode GaN p-channel MOSFETs for power integration. in 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD). 2020. IEEE.
    18. Chierchia, R., Strain and crystalline defects in epitaxial GaN layers studied by high-resolution X-ray diffraction. 2007, Universität Bremen.
    19. Morkoį, H., Handbook of nitride semiconductors and devices, Materials Properties, Physics and Growth. 2009: John Wiley & Sons.
    20. Ambacher, O., et al., Two-dimensional electron gases induced by spontaneous and piezoelectric polarization charges in N-and Ga-face AlGaN/GaN heterostructures. Journal of applied physics, 1999. 85(6): p. 3222-3233.
    21. Meneghini, M., et al., GaN-based power devices: Physics, reliability, and perspectives. Journal of Applied Physics, 2021. 130(18).
    22. Bernardini, F., V. Fiorentini, and D. Vanderbilt, Spontaneous polarization and piezoelectric constants of III-V nitrides. Physical Review B, 1997. 56(16): p. R10024.
    23. Vurgaftman, I. and J.n. Meyer, Band parameters for nitrogen-containing semiconductors. Journal of Applied Physics, 2003. 94(6): p. 3675-3696.
    24. Zoroddu, A., et al., First-principles prediction of structure, energetics, formation enthalpy, elastic constants, polarization, and piezoelectric constants of AlN, GaN, and InN: Comparison of local and gradient-corrected density-functional theory. Physical Review B, 2001. 64(4): p. 045208.
    25. Morkoc, H. and J. Leach, Polarization in GaN Based heterostructures and heterojunction field effect transistors (HFETs), in Polarization Effects in Semiconductors: From Ab InitioTheory to Device Applications. 2008, Springer. p. 373-466.
    26. Ambacher, O., et al., Polarization induced interface and electron sheet charges of pseudomorphic ScAlN/GaN, GaAlN/GaN, InAlN/GaN, and InAlN/InN heterostructures. Journal of Applied Physics, 2021. 129(20).
    27. Ambacher, O., et al., Role of spontaneous and piezoelectric polarization induced effects in Group‐III nitride based heterostructures and devices. physica status solidi (b), 1999. 216(1): p. 381-389.
    28. Shao, P., et al., High density polarization-induced 2D hole gas enabled by elevating Al composition in GaN/AlGaN heterostructures. Applied Physics Letters, 2023. 122(14).
    29. Abbas, T. and L. Slewa, Transmission line method (TLM) measurement of (metal/ZnS) contact resistance. Int. J. Nanoelectronics and Materials, 2015. 8: p. 111-120.
    30. Yan, W., et al., Analysis of the ohmic contacts of Ti/Al/Ni/Au to AlGaN/GaN HEMTs by the multi-step annealing process. Journal of Semiconductors, 2012. 33(6): p. 064005.
    31. Ho, J.-K., et al., Low-resistance ohmic contacts to p-type GaN. Applied Physics Letters, 1999. 74(9): p. 1275-1277.
    32. Jang, H.W., S.Y. Kim, and J.-L. Lee, Mechanism for ohmic contact formation of oxidized Ni/Au on p-type GaN. Journal of applied physics, 2003. 94(3): p. 1748-1752.
    33. Ho, J.-K., et al., Low-resistance ohmic contacts to p-type GaN achieved by the oxidation of Ni/Au films. Journal of Applied Physics, 1999. 86(8): p. 4491-4497.
    34. Chary, I., et al., Influence of surface treatment and annealing temperature on the formation of low-resistance Au/Ni ohmic contacts to p-GaN. Journal of electronic materials, 2009. 38: p. 545-550.
    35. Cao, Y. Methods to achieve Ohmic contact to p-GaN. in International Conference on Optoelectronic Materials and Devices (ICOMD 2021). 2022. SPIE.
    36. Li, X., et al., The significant effect of the thickness of Ni film on the performance of the Ni/Au Ohmic contact to p-GaN. Journal of Applied Physics, 2014. 116(16).
    37. Koide, Y., et al., Effects of annealing in an oxygen ambient on electrical properties of ohmic contacts to p-type GaN. Journal of electronic materials, 1999. 28: p. 341-346.
    38. Hashizume, T., et al., Effects of postmetallization annealing on interface properties of Al2O3/GaN structures. Applied Physics Express, 2018. 11(12): p. 124102.
    39. Zhang, J., et al., High-mobility normally OFF Al 2 O 3/AlGaN/GaN MISFET with damage-free recessed-gate structure. IEEE Electron Device Letters, 2018. 39(11): p. 1720-1723.
    40. Zhong, Y., et al., A review on the GaN-on-Si power electronic devices. Fundamental Research, 2022. 2(3): p. 462-475.
    41. A., S.K., et al., CMOS LOGIC FAMILIES FOR VLSI DESIGN. International Conference on Aerospace Sciences and Aviation Technology, 2003. 10(10th International Conference On Aerospace Sciences & Aviation Technology): p. 827-838.
    42. Li, J.-F., <Ch4,VLSI, Jin-Fu Li, EE, NCU.pdf>.
    43. VLSI Final 1b Pseudo NMOS - Ratioed Logic (1). 2013 [cited 2024 June 6th];
    44. <INEL 4207 - Spring 2011- C10_11.pdf>.
    45. Huang, H.-W. and Y.-H. Wang, Development of n-channel and p-channel AlGaN/GaN Heterostructure Field Effect Transistors, in Institute of Microelectronics(EE). 2023, National Cheng Kung University(NCKU).
    46. Cai, Y., et al., High-temperature operation of AlGaN/GaN HEMTs direct-coupled FET logic (DCFL) integrated circuits. IEEE electron device letters, 2007. 28(5): p. 328-331.
    47. Tang, G., et al., Digital integrated circuits on an E-mode GaN power HEMT platform. IEEE Electron Device Letters, 2017. 38(9): p. 1282-1285.

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