面對不斷革新的半導體先進製程技術，半導體供應鏈後段的晶圓測試同樣面臨挑戰，利用測試來找到缺陷元件以辨識出可靠度不足的電子元件變得愈發困難。面對晶圓廠以及測試廠的製程偏移而導致低良率晶圓，晶圓圖後處理是高階產品的晶片商常用的業界手法，利用統計方法產生的演算法，對測試數據進行圖像與數值的離群值檢驗，並將結果加工於晶圓圖上，避免可靠度不足的元件流入市場。

現存的晶圓圖後處理方法多基於條件式與單變量，它們被單獨或合併執行以應對製程偏移的情況，這樣做法的缺點是品質與成本的兩難。若施加過多的防護，雖能保障出貨產品的品質，但高誤宰率導致晶片成本上升；若疏於防護，將造成出貨產品的品質與可靠度具不確定性，客戶退貨的風險上升。本研究以機器學習演算法提出了一個新穎的晶圓圖後處理方法，可用於製程偏移事件，對數據進行結構分析後提供高準確率的解決方案。

結果顯示，我們的方法成功地逮捕到受製程偏移影響的特定區域。在高維資料下，可靠度不足的假性良品會以離群點呈現，本研究首先使用特徵選取手法，再以支援向量機篩選出離群點，同時提出考量報廢成本與客戶退貨風險成本的利潤最佳化決策，最終，以資料群聚方法對不同失效模式進行分群，以此分揀出隨機失效原件與製程偏移導致的失效原件。此方法可以補足一般晶圓測試與晶圓圖產生手法的不足，預測結果可用於晶圓圖後處理，除了測試不良品之外，篩選出可靠度不足之產品也不會流入市場。

As fast evolution of advanced semiconductor process, it becomes much more difficult to capture defects and less reliable parts by wafer testing. To improve the quality guard band, statistical post-processing (SPP) methods have been developed based on test results. SPP technique, as a common industrial practice for chip suppliers, is a must for high-quality devices against process excursion.

In current practice, most of SPP methods are condition-based and univariate. They can be applied individually or sequentially against process variation or excursion. This can lead to overkill when the test result is complicated, or from the non-optimal parameters setting in SPP methods. Regarding the balance between quality and cost, our research proposes a dynamic post-processing methodology against process excursion, based on statistical techniques and machine learning, to provide a single and high precision solution for quality guard band.

We propose a procedure for structural analysis of wafers manufactured during the process excursion period. Using the multivariate data of wafer sort, we apply support vector machine to detect less-reliable devices after important feature selection. Our results clearly demonstrate that the known process issues (STI height non-uniformity / Poly stringer) are successfully captured by our algorithm, as shown in the edge fails. High coverage is reflected on typical wafer process variation and probing path due to contact resistance. Then, data clustering approaches are applied to extract our target, process excursion area. Based on our prediction, a decision making model to maximize profits and returns is also proposed. After that, wafer map post-processing can be applied to filter out less reliable devices.

Abdi, H. and Williams, L. J. (2010). Principal component analysis. Wiley Interdisciplinary Reviews: Computational Statistics, 2(4):433–459.
Automotive Electronics Council, C. T. C. (2011). Guidelines for part average testing. AEC - Q001 Rev-D.
Automotive Electronics Council, C. T. C. (2012). Guidelines for statistical yield analysis. AEC - Q002 Rev B.
Butler, K. M., Subramaniam, S., Nahar, A., Carulli, J. M., Anderson, T. J., and Daasch, W. R. (2006). Successful development and implementation of statistical outlier techniques on 90nm and 65nm process driver devices. In 2006 IEEE International Reliability Physics Symposium Proceedings, pages 552–559.
Chang, C. L. and Wen, C. H. . (2015). Demystifying IDDQ data with process variation for automatic chip classification. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(6):1175–1179.
Chen, H. H., Hsu, R., Yang, P., and Shyr, J. J. (2013). Predicting system-level test and in-field customer failures using data mining. In 2013 IEEE International Test Conference (ITC), pages 1–10.
Daasch, W. R. and Madge, R. (2005a). Data-driven models for statistical testing: Measurements, estimates and residuals. In IEEE International Conference on Test, 2005., pages 10 pp.–322.
Daasch, W. R. and Madge, R. (2005b). Variance reduction and outliers: Statistical analysis of semiconductor test data. In IEEE International Conference on Test, 2005., pages 9 pp.–312.
Daasch, W. R., McNames, J., Madge, R., and Cota, K. (2002). Neighborhood selection for IDDQ outlier screening at wafer sort. IEEE Design Test of Computers, 19(5):74–81.
Drmanac, D., Sumikawa, N., Winemberg, L., Wang, L., and Abadir, M. S. (2011). Multidimensional parametric test set optimization of wafer probe data for predicting in field failures and setting tighter test limits. In 2011 Design, Automation Test in Europe, pages 1–6.
Ester, M., Kriegel, H.-P., Sander, J., Xu, X., et al. (1996). A density-based algorithm for discovering clusters in large spatial databases with noise. In KDD, volume 96, pages 226–231.
Ferhani, F., Saxena, N. R., McCluskey, E. J., and Nigh, P. (2008). How many test patterns are useless? In 26th IEEE VLSI Test Symposium (vts 2008), pages 23–28.
Friedman, J. (1997). On bias, variance, 0/1 - loss, and the curse-of-dimensionality. Data Min. Knowl. Discov., 1:55–77.
Haensch, W., Nowak, E. J., Dennard, R. H., Solomon, P. M., Bryant, A., Dokumaci, O. H., Kumar, A., Wang, X., Johnson, J. B., and Fischetti, M. V. (2006). Silicon CMOS devices beyond scaling. IBM Journal of Research and Development, 50(4.5):339–361.
Hessinger, U., Chan, W., Schafman, B., Nguyen, T., and Burt, S. (2013). Statistical correlation of inline defect to sort test in semiconductor manufacturing. In ASMC 2013 SEMI Advanced Semiconductor Manufacturing Conference, pages 212–219.
Hsieh, Y., Tzeng, G., Lin, G. T., and Yu, H. (2010). Wafer sort bitmap data analysis using the PCA-based approach for yield analysis and optimization. IEEE Transactions on Semiconductor Manufacturing, 23(4): 493–502.
Hu, X., Pan, W., Shi, Z., Yan, X., and Ma, T. (2010). Testing structure for detection of poly stringer defects in CMOS ICs. Tsinghua Science and Technology, 15(3):347–351.
Kumar, R. (2007). The business of scaling. IEEE Solid-State Circuits Society Newsletter, 12(1):22–26.
Lakin, D. R. and Singh, A. D. (1999). Exploiting defect clustering to screen bare die for infant mortality failures: An experimental study. In International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), pages 23–30.
Liu, C.-W. and Chien, C.-F. (2013). An intelligent system for wafer bin map defect diagnosis: An empirical study for semiconductor manufacturing. Engineering Applications of Artificial Intelligence, 26(5):1479 – 1486.
Liu, M., Pan, R., Ye, F., Li, X., Chakrabarty, K., and Gu, X. (2018). Fine-grained adaptive testing based on quality prediction. In 2018 IEEE International Test Conference (ITC), pages 1–10.
Lloyd, J., Clemens, J., and Snede, R. (1999). Copper metallization reliability. Microelectronics Reliability, 39(11):1595 – 1602.
MacQueen, J. et al. (1967). Some methods for classification and analysis of multivariate observations. In Proceedings of the fifth Berkeley symposium on mathematical statistics and probability, volume 1, pages 281–297. Oakland, CA, USA.
Madge, R. (2005). New test paradigms for yield and manufacturability. IEEE Design Test of Computers, 22(3): 240–246.
Mann, W. R. (2008). Wafer test methods to improve semiconductor die reliability. IEEE Design & Test of Computers, 25(6):528–537.
Mann, W. R. (2008). Wafer test methods to improve semiconductor die reliability. IEEE Design Test of Computers, 25(6):528–537.
Maxwell, P. C., Aitken, R. C., Johansen, V., and Inshen Chiang (1991). The effect of different test sets on quality level prediction: When is 80% better than 90%? In 1991, Proceedings. International Test Conference, pages 358–.
McCluskey, E. J. and Buelow, F. (1989). IC quality and test transparency. IEEE Transactions on Industrial Electronics, 36(2):197–202.
Platt, J. C. (1999). Probabilistic outputs for support vector machines and comparisons to regularized likelihood methods. In ADVANCES IN LARGE MARGIN CLASSIFIERS, pages 61–74. MIT Press.
Powell, T. J., Pair, J., St. John, M., and Counce, D. (2000). Delta IDDQ for testing reliability. In Proceedings 18th IEEE VLSI Test Symposium, pages 439–443.
Rao, L., Bushnell, M. L., and Agrawal, V. D. (2003). New graphical IDDQ signatures reduce defect level and yield loss. In 16th International Conference on VLSI Design, 2003. Proceedings., pages 353–360.
Riordan, W. C., Miller, R., and St Pierre, E. R. (2005). Reliability improvement and burn in optimization through the use of die level predictive modeling. In 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual., pages 435–445.
Robinson, K., DeVriendt, K., and Evans, D. (2004). Integration issues of cmp. In Chemical-Mechanical Planarization of Semiconductor Materials, pages 351–417. Springer.
Sabade, S. and Walker, D. M. H. (2001). Improved wafer-level spatial analysis for IDDQ limit setting. In Proceedings International Test Conference 2001 (Cat. No.01CH37260), pages 82–91.
Schölkopf, B., Williamson, R., Smola, A., Shawe-Taylor, J., and Platt, J. (1999). Support vector method for novelty detection. In Proceedings of the 12th International Conference on Neural Information Processing Systems, NIPS’99, pages 582–588, Cambridge, MA, USA. MIT Press.
Singh, A. D. and Krishna, C. M. (1991). On optimizing wafer-probe testing for product quality using die-yield prediction. In 1991, Proceedings. International Test Conference, pages 228–.
Singh, A. D., Nigh, P., and Krishna, C. M. (1997). Screening for known good die (KGD) based on defect clustering: An experimental study. In Proceedings International Test Conference 1997, pages 362–369.
Singh, D., Lakin, D. R., and Nigh, P. (1998). Binning for IC quality: Experimental studies on the sematech data. In Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223), pages 4–10.
Skinner, K. R., Montgomery, D. C., Runger, G. C., Fowler, J. W., McCarville, D. R., Rhoads, T. R., and Stanley, J. D. (2002). Multivariate statistical methods for modeling and analysis of wafer probe test data. IEEE Transactions on Semiconductor Manufacturing, 15(4):523–530.
Stratigopoulos, H. (2018). Machine learning applications in IC testing. In 2018 IEEE 23rd European Test Symposium (ETS), pages 1–10.
Stratigopoulos, H. and Streitwieser, C. (2018). Adaptive test with test escape estimation for mixed-signal ICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(10):2125–2138.
Sumikawa, N., Drmanac, D., Wang, L., Winemberg, L., and Abadir, M. S. (2011). Important test selection for screening potential customer returns. In Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, pages 1–4.
Sumikawa, N., Tikkanen, J., Wang, L., Winemberg, L., and Abadir, M. S. (2012). Screening customer returns with multivariate test analysis. In 2012 IEEE International Test Conference, pages 1–10.
Tax, D. M. and Duin, R. P. (2004). Support vector data description. Machine Learning, 54(1):45–66.
Thibeault, C. and Hariri, Y. (2009). C∆Iddq: Improving current-based testing and diagnosis through modified test pattern generation. IEEE transactions on very large scale integration (VLSI) systems, 19(1):130–141.
Turakhia, R., Benware, B., Madge, R., Shannon, T., and Daasch, R. (2005). Defect screening using independent component analysis on IDDQ. In 23rd IEEE VLSI Test Symposium (VTS’05), pages 427–432.
Wang, L. (2017). Experience of data analytics in EDA and test - principles, promises, and challenges. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 36(6):885–898.