成功大學博碩士論文系統

簡易檢索 / 詳目顯示

回結果列表

研究生：	許宇森 Hsu, Yu-Sen
論文名稱：	運用TCAD研究LDMOS及LIGBT功率元件應用在ESD放電上之特性 TCAD Simulation-Based Study on LDMOS and LIGBT Power Devices Application on ESD Discharging
指導教授：	江孟學 Chiang, Meng-Hsueh
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 奈米積體電路工程碩士博士學位學程 MS Degree/Ph.D. Program on Nano-Integrated-Circuit Engineering
論文出版年：	2020
畢業學年度：	108
語文別：	英文
論文頁數：	64
中文關鍵詞：	TCAD 、橫向擴散金屬氧化物半導體、絕緣閘雙極性電晶體、閘流體、靜電放電、ESD靜電防護電路
外文關鍵詞：	TCAD, LDMOS, LIGBT, SCR, ESD, ESD Protection Circuit
相關次數：	點閱：140 下載：35
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

靜電放電(Electrostatic Discharge, ESD)，是積體電路可靠度的一個重要問題。在互補式金氧半(CMOS)積體電路中，CMOS元件因為先進製程的發展不斷縮小，但外界環境中的靜電並未減少，即使把ESD元件的尺寸加大，ESD防護能力不見得會成正比提昇，使得深次微米CMOS積體電路對靜電放電的防護能力下降，因此一個有效的ESD靜電防護電路廣泛的被研究。
有關ESD靜電防護電路中的核心ESD元件，其I-V特性曲線操作範圍，為ESD防護能力的重要指標，故本篇論文旨在探討利用TCAD軟體模擬LDMOS元件在其不同的結構參數下,包含1.Gate Bias Region 2.Well Depth 3. Width、Junction Length and Depth 4.Drift Length and Drift Concentration之I-V特性影響。其他額外加入成本較高的修正包含Gate bias和STI，以及一個新型結構3D LDMOS-LIGBT-SCR元件，最後帶入SOI結構中Gate和Back Gate之研究。本篇論文完整說明和呈現模擬結果，並統整結論和設計準則，以期能設計出符合Safe Design Window之元件，並將模擬成果提供未來實際設計元件之參考。

Electrostatic discharge (ESD) is an important issue in the reliability of integrated circuits. In the CMOS circuit, each single device has continuously shrunk due to the development of advanced manufacturing processes, but the electrostatic charge in the external environment has not been reduced. Even if the size of the ESD device is increased, the ESD protection ability will not be proportionally improved. As a result, the protection of deep sub-micron CMOS integrated circuits against ESD would be reduced. Therefore, an effective ESD protection circuit has been widely studied.
There is a core ESD device in the ESD protection circuit, and its I-V characteristics within needed operating range are important indicators of ESD protection capabilities. Therefore, this thesis aims to discuss the I-V characteristics of LDMOS in its different 1. Gate Bias Region 2. Well Depth 3. Width, Junction Length and Depth 4. Drift Length and Drift Concentration by using TCAD software. The additional high-cost amendments include Gate bias and STI as well as a new structure with 3D LDMOS-LIGBT-SCR. Finally, we bring the thesis into the Back Gate study within the SOI structure. This thesis fully presents the simulation results and summarizes the conclusions and guidelines to design the ESD devices that meet the Safe Design Window. Also, the simulation results will provide a good reference for future actual design.

摘要 I
Abstract II
致謝 III
Contents V
Table Captions VII
Figure Captions VII
Chapter 1 Introduction 1
1 ESD Concept 1
2 ESD Discharge Model [2] 1
3 ESD Protection Circuit [4] 4
4 Motivation 5
5 Overview of the Thesis 6
Chapter 2 ESD Device and Breakdown Theory 7
1 Avalanche Breakdown [5] 7
2 ESD Device Introduction 8
2.1 Basis Device Introduction	8
2.2 The Most Important ESD Device – SCR [5] 10
3 PNPN Structure Operation Intervals [5] 14
3.1 (0)-(1) Forward Blocking 14
3.2 (1)-(2) Negative-Resistance Region 17
3.3 (2)-(3) Forward Conduction 19
4 ESD Device Using in this Thesis 19
Chapter 3 Device Design and Considerations 22
1 Configuration 22
1.1 Device Configuration 22
1.2 Circuit Configuration 24
2 Preliminary Knowledge Concept Preview 26
3 Device Structure Design 30
3.1 Gate Bias Position 30
3.2 Well Depth 34
3.3 Width, Junction Length and Depth 37
3.4 Drift Length and Concentration 42
4 Summary 44
Chapter 4 Design Optimization and Temperature Effect 45
1 Gate Bias and STI 45
2 3D LDMOS-LIGBT-SCR 51
3 SOI Structure – Gate & Back Gate Bias 52
4 Temperature Effect 56
5 Device Design for Safe Design Window 58
Chapter 5 Conclusion 62
References 63
                                    

[1] A. Amerasekera and C. Duvvury, "The impact of technology scaling on ESD robustness and protection circuit design," in IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A, vol. 18, no. 2, pp. 314-320, June 1995.
[2] Chua-Hsiang Pan,“Improved the ESD capability of 0.5μm high voltage device, Semiconductor Material and Process Equipment College of Engineering National Chiao Tung University for the Degree of Master of Science, February 2012.
[3] Jung-Hoon Chun, ESD Protection Circuits for Advanced CMOS Technologies, the department of electrical engineering and the committee on graduate studies of stanford university for the degree of doctor of philosophy, June 2006.
[4] Ming-Dou Ker, Chung-Yu Wu, Tao Cheng, M. J. -. Wu, T. -. Yu and A. C. Wang, "Whole-chip ESD protection for CMOS VLSI/ULSI with multiple power pins," Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS), Lake Tahoe, CA, USA, 1994, pp. 124-128.
[5] Sze, S. M. Physics of Semiconductor Devices, 2th ed. New York:John Wiley & Sons,1981.
[6] Ajith Amerasekera and Charvaka Duvvury, ESD in Silicon Integrated Circuits, 2nd Edition, John Wiley & Sons, Ltd, 2002.
[7] 楊叡霖, "使用TCAD實現靜電放電防護元件電導調變之暫態分析, "逢甲大學電子工程學系碩士論文,May 2016.
[8] Wen-Yi Chen, Ming-Dou Ker, Yeh-Jen Huang, Yeh-Ning Jou and Geeng-Lih Lin, "Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration," APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, Macao, 2008, pp. 61-64.
[9] J. L. Moll, M. Tanenbaum, J. M. Goldey and N. Holonyak, "P-N-P-N Transistor Switches," in Proceedings of the IRE, vol. 44, no. 9, pp. 1174-1182, Sept. 1956.
[10] 游信強, "日四技實務專題報告DRIFT飄移區之長度對LDMOS-800V高壓元件之研究(700~900V), "國立勤益科技大學電子工程系碩士論文, January 2011.
[11] 簡鳳佐, 功率金氧半電晶體(Power MOSFET)之簡介, 逢甲大學電子系專輯報導, 2014.
[12] Chia-Wei Hung, Design and Implementation of 700V LIGBT for Power IC Application, Institute of Electrical Engineering and Computer Science National Chiao Tung University for the Degree of Master of Science, July 2005.

校內：立即公開
校外：立即公開

簡易檢索 / 詳目顯示

相關論文