氮氧化鋅(ZnON)通道層與源/汲極(S/D)金屬之搭配極為重要，一旦特徵接觸電阻(Specific contact resistance, ρ_c)以及源/汲極串聯電阻(Source/Drain resistance, R_SD)過高，將嚴重減損ZnON導通電流。為降低S/D串聯電阻、提升ZnON薄膜電晶體(ZnON TFTs)之閘極控制力、抑制閘極漏電電流與降低操作電壓，本論文引入氧化鋁鋅(AZO)緩衝層(Buffer layer, BL)於主動層及源/汲之間，利用穿隧效應大幅降低R_SD，並以共濺鍍法開發氧化矽鉿高介電係數材料作為閘極介電層，提升元件電特性。
本研究分為三大部分，第一部分為S/D金屬之選擇，探究其與半導體接觸之特徵接觸電阻。利用環形傳輸線性量測(CTLM)金屬與ZnON及AZO之ρ_c，並藉由所製備TFT之元件電特性萃取R_SD並比較進行分析。實驗結果顯示，於鎳、鈦與鋁幾種金屬中，鋁金屬擁有最較佳接觸特性。第二部分固定S/D為鋁金屬，引入AZO BL，並成功利用調變沉積壓力來改變AZO薄膜包括載子移動率、載子濃度與電阻率等之材料特性。據XPS薄膜分析結果顯示，利用不同之沉積壓力可調整AZO薄膜之氧空缺濃度。歸納於不同沉積壓力製備AZO薄膜量測所得ρ_c與霍爾量測結果顯示，以4 mTorr沉積之AZO薄膜量可擁有最高載子濃度與最低ρ_c。另於4 mTorr沉積所得不同層厚AZO薄膜的TFT元件特性分析結果顯示，數據顯示AZO薄膜厚度為25 nm時，元件擁有最佳特性。第三部分進一步分析熱退火對AZO緩衝層材料特性與ρ_c之影響及其對應用於ZnON TFT元件電特性與R_SD之影響。
本論文於第一部分探討不同S/D金屬對於ZnON通道層ρ_c之影響及其與TFT電特性與R_SD關係之研究結果顯示，於鎳、鈦與鋁三種金屬中，鋁應為最佳S/D金屬。ρ_c分別為鎳金屬之1.17×10-2 Ω-cm2、鈦金屬之2.47×10-3 Ω-cm2以及鋁金屬之與4.35×10-4 Ω-cm2，而R_SD由49.4 kΩ下降至28.2 kΩ，歸功於Al S/D與ZnON兩種材料間有較低的功函數差異。
於第二部分為AZO BL之製備及材料分析研究結果方面，於藉由濺鍍系統製程壓力調變AZO薄膜之載子濃度、載子移動率及電阻率之實驗上，利用4、6、8與12 mTorr沉積之AZO薄膜，依據CTLM及霍爾量測輔以XPS分析，確認4 mTorr沉積之AZO薄膜擁有最高氧空缺比例(53.2 %)，展現最高濃度(3.8×1020 cm-3)與最低電阻率(6.42×10-3 Ω-cm)，因薄膜之Al成分比例較高。於緩衝層最適化薄膜厚度探討上，實驗結果顯示於4 mTorr沉積壓力條件所製備膜厚度為25-nm-AZO緩衝層於TFT應用可使元件擁有最佳特性(其μ_FE、SS、I_on/I_off、V_TH與I_on分別為28.1 cm2/V∙s、86 mV/dec、3.01×107、0.2 V與1.12×10-4 A)。
於第三部份有關熱退火溫度(100 oC、200 oC與300 oC)對AZO緩衝層材料特性與ρ_c之影響及其對應用於ZnON TFT元件電特性與R_SD之影響研究方面，證實進一步退火處理AZO BL可提升濃度並同時降低電阻率，由未退火之3.8×1020 cm-3與6.42×10-3 Ω-cm優化至PDA 300 ºC之5.87×1020 cm-3與1.81×10-3 Ω-cm。於TFT應用上，熱退火除了降低ρ_c亦更進一步降低TFT元件之R_SD，提高導通電流(I_on)，大幅優化元件特性，由Device A1之8.7 kΩ與1.12×10-4 A優化至Device B25-300 之5.97 kΩ與2.83×10-4。實驗結果顯示，選用鋁作為S/D金屬，確實可降低電極與薄膜之R_c與ρ_c，亦減少R_SD。使用緩衝層於S/D與通道層間，不但可大幅降低S/D接觸之ρ_c與TFT之元件電特性與R_SD。相較w/o PDA之元件，應用經300 oC熱退火處理AZO緩衝層於ZnON TFTs可擁有現較佳的元件特性，其載子移動率由28.1提升至35.9 cm2/V∙s、次臨界擺幅由86降為84 mV/dec、元件電流開關比由3.01×107增為7.26×107、臨界電壓由0.2變為0.16 V。
本論文利用不同沉積壓力製備AZO BL應用於ZnON薄膜電晶體之研究，於利用退火緩衝層降低ρ_c、R_SD、大幅提升導通電流與電流開關比等TFT元件特性之實驗結果，預期將有助於OLED先進顯示技術之應用以及面板性能之提升。

In regular ZnON TFTs, the device properties show high contact resistance between the source/drain (S/D) electrode, which decreases turn-on current (I_on), Subthreshold Swing (SS), and low mobility. In this work, reducing the resistance between the S/D and channel layer (R_SD) with better performance of ZnON device by tunneling effect with aluminum zinc oxide (AZO) buffer layer (BL) between S/D and channel. In order to improve the electrical properties of ZnON TFTs with hafnium silicon oxide (Hf0.86Si0.14O) as gate dielectrics and use sputtering deposited high concentration (> 1020 cm-3) AZO BL. For investing contact resistance (R_c) of S/D with ZnON and AZO BL, use circular transmission line measurement (CTLM). It can get R_c and specifitic resistance (ρ_c). Experimental results reveal that AZO BL was deposited at power 60 W in 4 mTorr chamber pressure by post deposition annealing (PDA) in N2 at 300 ºC shows the best device performance such as the on/off current ratio of 7.26×107, the I_on of 2.83×10-4 A, the mobility (μ_FE) of 35.9 cm2V-1s-1, the SS of 84 mV/dec, the ρ_c of 5.83×10-5 Ω-cm2, and the R_SD of 5.97 kΩ, respectively.

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